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  • Description The latest forum discussions for Arm architectures and Cortex-A, R, M, and classic processors.
  • Threads 3593 Questions
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  • Not Answered

    VMSAv8-64 - How to change 2-stage translation table descriptors of a given VMID and do invalidation afterwards? 0

    • AArch64
    • Armv8-A
    4888 views
    2 replies
    Latest over 8 years ago
    by Jorge
  • Answered

    Can Cortex-A53 l2 cache be controlled seperatly? 0

    • Cortex-A53
    • Cortex-A
    6727 views
    2 replies
    Latest over 8 years ago
    by Emmy0
  • Answered

    R5 DSM tarmac format <time> <scale> option 0

    3605 views
    1 reply
    Latest over 8 years ago
    by Peter Rielly Arm Employee Badge
  • Answered

    Is that possible for Cortex-R5's dual-core to handle interrupt during lock-step mode? +1

    • Cortex-R
    7089 views
    4 replies
    Latest over 8 years ago
    by AJ
  • Answered

    Cortex-M7 minimum schematic ? +1

    • Cortex-M7
    • Cortex-M
    8044 views
    4 replies
    Latest over 8 years ago
    by reha
  • Answered

    Optimized RGB to YCbCr conversion on Cortex-M7 +1

    • Cortex-M7
    • Cortex-M
    4804 views
    1 reply
    Latest over 8 years ago
    by Jens Bauer
  • Suggested Answer

    How do I program a prefix on my ARM 32-bit Cortex V3.10? 0

    5377 views
    1 reply
    Latest over 8 years ago
    by Jens Bauer
  • Suggested Answer

    Constant power supply with countdown timer triggered by a momentary switch 0

    3818 views
    1 reply
    Latest over 8 years ago
    by Jens Bauer
  • Answered

    Cache attribute write back/write allocate for Cortex-M4 +1

    • Cortex-M
    • Cortex-M4
    21320 views
    5 replies
    Latest over 8 years ago
    by dongyanxia
  • Answered

    CAT Cache Allocation Technology) and CDP (code and Data Prioritization) features support +1

    • Cache
    5445 views
    2 replies
    Latest over 8 years ago
    by 42Bastian Schick
  • Suggested Answer

    GIC order of completion of interrupts 0

    • Generic Interrupt Controller
    5989 views
    4 replies
    Latest over 8 years ago
    by josecm
  • Suggested Answer

    What's the relationship between exclusive access and memory cacheable in Cortex A53? 0

    • Cortex-A53
    • Armv8-A
    • Cortex-A
    6766 views
    3 replies
    Latest over 8 years ago
    by Emmy0
  • Not Answered

    A9 Code after vector table 0

    • Cortex-A9
    • Cortex-A
    • TrustZone
    9693 views
    8 replies
    Latest over 8 years ago
    by 42Bastian Schick
  • Answered

    Armv8 Memory Mapping 0

    • Cortex-A53
    • Cortex-A57
    • Armv8-A
    • Cortex-A
    8922 views
    7 replies
    Latest over 8 years ago
    by 42Bastian Schick
  • Not Answered

    Cortex A8 PLD 0

    • Cortex-A
    • Cortex-A8
    4279 views
    1 reply
    Latest over 8 years ago
    by 42Bastian Schick
  • Answered

    Which component will program TZASC? 0

    • Armv7-A
    • TrustZone
    9232 views
    5 replies
    Latest over 8 years ago
    by raghu.ncstate
  • Answered

    Suitable ARM processor for Traffic Lights Controller 0

    • Cortex-M
    • C
    5581 views
    2 replies
    Latest over 8 years ago
    by Nikl@s
  • Answered

    Why do we need atomicity in ARM Architecture? 0

    • Cortex-A
    • Armv8.1-A
    9027 views
    5 replies
    Latest over 8 years ago
    by daith
  • Answered

    Which component will program TZASC? 0

    • ACE
    • AXI
    • TrustZone
    • Armv8-M
    • Secure Transactions
    • Memory
    9122 views
    2 replies
    Latest over 8 years ago
    by Sahil
  • Suggested Answer

    Development in Assembly Language +1

    • Toolchain
    • Raspberry Pi
    • Cortex-A57
    • Raspberry Pi 3
    • Armv8
    • Arm Assembly Language (ASM)
    • C
    10117 views
    5 replies
    Latest over 8 years ago
    by AnthonyPaulO
<>
Topics being discussed in this forum
  • AArch64
  • AMBA
  • Arm Assembly Language (ASM)
  • Armv7-A
  • Armv8-A
  • Armv8-M
  • AXI
  • Cache
  • Cortex-A
  • Cortex-A53
  • Cortex-A7
  • Cortex-A8
  • Cortex-A9
  • Cortex-M
  • Cortex-M0
  • Cortex-M3
  • Cortex-M4
  • Cortex-M7
  • Cortex-R
  • Interrupt
  • Linux
  • Memory
  • Memory Management Unit (MMU)
  • NEON
  • TrustZone