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  • Description The latest forum discussions for Arm architectures and Cortex-A, R, M, and classic processors.
  • Threads 3618 Questions
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  • Not Answered

    Why LDREX instruction trigger Hard Fault in Cortex-M7 0

    2246 views
    1 reply
    Latest over 3 years ago
    by Annie
  • Answered

    Time measurement using Performance Monitors Register on Cortex-A72 0

    • Cortex-A72
    4067 views
    2 replies
    Latest over 3 years ago
    by Chanh
  • Not Answered

    ISR should disable interrupts or does the ARM processor do it automatically when interrupt comes from a peripheral 0

    • Interrupt Handling
    • Embedded Linux
    2101 views
    1 reply
    Latest over 3 years ago
    by Martin Weidmann Arm Employee Badge
  • Suggested Answer

    flush_dcache_range equivalent in arm64 0

    • Cache coherency
    • Cache Memory Devices
    • Arm64
    • Memory Architecture
    6301 views
    1 reply
    Latest over 3 years ago
    by Willy Wolff Arm Employee Badge
  • Answered

    Are there any ARM processors with hardware H.264 encoder? Other than i.MX 6 0

    4132 views
    7 replies
    Latest over 3 years ago
    by Niju K Jacob
  • Not Answered

    Where do I downlad the document 'ARM Power Control System Architecture Specification' ? +1

    1802 views
    1 reply
    Latest over 3 years ago
    by Zenon (Zhilong) Xiu Arm Employee Badge
  • Answered

    Understanding deeply ARM Processors Architetures +1

    • Arm Training
    1446 views
    2 replies
    Latest over 3 years ago
    by Oliveira
  • Answered

    Compiler options for Cortex-R52 CoreMark 0

    4526 views
    5 replies
    Latest over 3 years ago
    by 42Bastian Schick
  • Answered

    How to obtain ARMv8 CPU is secure or non-secure under EL1? 0

    • Kernel Developers
    • Armv8-A
    • TrustZone
    3623 views
    5 replies
    Latest over 3 years ago
    by Emmy0
  • Not Answered

    AXI4 0

    1062 views
    0 replies
    Started over 3 years ago
    by Sabrine BAAOUNI
  • Not Answered

    Where I can get the TAP ID? 0

    • JTAG
    • SWD
    • Debug Access Port (DAP)
    2354 views
    1 reply
    Latest over 3 years ago
    by Annie
  • Not Answered

    Arm Atomic instructions 0

    1478 views
    1 reply
    Latest over 3 years ago
    by Martin Weidmann Arm Employee Badge
  • Answered

    IO coherency 0

    2464 views
    1 reply
    Latest over 3 years ago
    by vstehle Arm Employee Badge
  • Not Answered

    In CHI spec,why normal and device memory addr aligned rule are diffrent? 0

    • CHI
    • Memory Architecture
    1327 views
    0 replies
    Started over 3 years ago
    by Furance
  • Not Answered

    R52 Development Boards +1

    • Cortex-R52
    • Development Boards
    • Software Development
    4373 views
    1 reply
    Latest over 3 years ago
    by SarahW
  • Not Answered

    STM32 F411RE SPI4 Pins Not Working 0

    2139 views
    2 replies
    Latest over 3 years ago
    by DJSG
  • Not Answered

    s802 2.0ghz mali 450 0

    943 views
    0 replies
    Started over 3 years ago
    by squawk2003
  • Answered

    I have a question about cache operations. +1

    2188 views
    5 replies
    Latest over 3 years ago
    by YP.Lu
  • Not Answered

    Devices that Implement and Develop ARM Trustzone 0

    1993 views
    2 replies
    Latest over 4 years ago
    by Hayes169
  • Not Answered

    LDR instruction not executing 0

    • 5 (BusFault)
    • 3 (HardFault)
    • Compilers
    • Cortex-M4
    3638 views
    3 replies
    Latest over 4 years ago
    by alexxs88
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