Good morning
I design a SOC which already includes a Cortex M7 and a Coresight SOC400 TPIU in order to support multiple trace sources.
Is there a way to add the SWO feature in the design beside adding the full Cortex-M7 TPIU as well?
Beside the Coresight SOC400 TRM and the M7 TRM I found the following information:
ttps://developer.arm.com/documentation/ka004877/1-0/?lang=en
Is there some kind of SWO (only) IP as implied in https://developer.arm.com/documentation/ddi0314/h/?lang=en
I cannot find anything like that in more recent documentation.