A bit of background at a high level. The SoC I'm working on has M7 and A53 cores. I have 2 shared memory sections as uncacheable regions in SRAM. Also, the shared memory sections are configures as volatile access. I'm trying to copy 32 bytes using memcpy(). I'm getting a data abort exception when trying to do the store operation(stp) as shown below.
Looking at the exception registers, I see the following.
The exception always happens with the same instruction. My understanding is that unaligned accesses are allowed.
Anyone have any thoughts on this?
The ESR_EL1.ISS.DFSC field is reporting an alignment fault (Arm Armv9-A Architecture Registers). If the address is marked as Device, or if you have strict alignment checking enabled, you'll need to have the address aligned to the element size. So to 64 bits/8 bytes. It looks like your STP address is only 4-byte aligned.
Martin Weidmann Does that mean on a 64 bit core, destination address must always be aligned to 64 bits?
As Martin writes: It depends. The manual lists the cases.
There's more of an explanation here: Learn the architecture: AArch64 memory model (arm.com)