Hi,
Can sw do BP maintenance on CA55 core?
If can not, how can the core guarantee that branch prediction will not cause unpredictable error ？e.g. speculative access to illegal address?
The architecture prohibits speculative instruction fetch from locations marked as no-access or XN. As such, Cortex-A55 will not speculatively fetch instructions from locations the MMU / page-tables have been configured not to.
The Architecture Reference Manual section on "Concurrent modification and execution of instructions" provides details on the maintenance sequences required to synchronize instruction code updates.
Best regards, Simon.