Arm IRQ handler will call the ISR via like this (See the asterisk mark in below code):
IRQ_Handler
PUSH {r0-r3, r12, lr} @ Store AAPCS registers and LR onto the IRQ mode stack
BL @ identify_and_clear_source
BL @ C-irq_handler *****
POP {r0-r3, r12, lr} @ Restore registers and
SUBS pc, lr, #4 @ return from exception using modified LRSo it means Linux ISR or ISR only disabling the interrupt ? And until ISR disable the interrupt line ,will ARM receive interrupt from others peripheral ?Also untill we clear the interrupt at ISR , can ARM will receive one more interrupt on same INTR line ?Regards
Are you work with A/R profile devices or M profile devices?
Assuming A or R (as that's what I'm familiar with), then on taking an interrupt exception the interrupt mask(s) will be set in CPSR (or PSTATE in AArch64).For v7/AArch32,try this for further reading:ARM Cortex-A Series Programmer's Guide for ARMv7-A (chapter on exception priorities)