about tail chaning of Cortex-M0

Hi,

have you referred to the https://community.arm.com/docs/DOC-2607 ?

It would be very helpful.

I think the mechanism of Cortex-M0's tail chainning is the same as Cortex-M4's.

The difference of the interrupt latencies would come from the differences of the internal bus architecture.

Cortex-M3/M4 has two AHB Lite buses for instructions and data, and instructions and data can be accessed simultaneously.

However Cortex-M0 has only one AHB Lite bus and a confliction between instruction and data accesses would cause extra latencies.

Best regards,

Yasuhiko Koumoto.

Hi,

have you referred to the https://community.arm.com/docs/DOC-2607 ?

It would be very helpful.

I think the mechanism of Cortex-M0's tail chainning is the same as Cortex-M4's.

The difference of the interrupt latencies would come from the differences of the internal bus architecture.

Cortex-M3/M4 has two AHB Lite buses for instructions and data, and instructions and data can be accessed simultaneously.

However Cortex-M0 has only one AHB Lite bus and a confliction between instruction and data accesses would cause extra latencies.

Best regards,

Yasuhiko Koumoto.

Hi, yasuhiko.

Thank you for your reply.

I read the page you mentioned once, but I was not ble able not to understand very well.

I’m not familiar with micro controllers, especially about the data bus.

I will keep trying to understand deeply what is written on that page.

Thank you again.

差出人: yasuhikokoumoto

日時: 2016年4月28日 13:59

宛先: 下田敏郎

件名: Re:  - about tail chaning of Cortex-M0

about tail chaning of Cortex-M0

reply from yasuhikokoumoto in ARM Processors - View the full discussion

Hello shimochan,

do you want to know what is the tail chaining?
If it is correct, the tail chaining means that preveios context POP and a new context PUSH will be omitted if the CPU detect another interrupt before POPing the contexts.
As you know one interrupt sequence takes as the following procedure.

<1> Detect Interrupt
<2> Push contexts (r0-r3, r12,r14, r15 and xPSR)
<3> Jump to ISR
<4> Process ISR
<5> Pop contexts (r0-r3, r12,r14, r15 and xPSR)
<6> Return to the interrupted position

If the next interrupt detects at the <5> or later, the sequence wil be the following.

<1> Detect Interrupt
<2> Push contexts (r0-r3, r12,r14, r15 and xPSR)
<3> Jump to ISR
<4> Process ISR
<5> Pop contexts (r0-r3, r12,r14, r15 and xPSR)
<*> New Interrupt
<6> Push contexts (r0-r3, r12,r14, r15 and xPSR)
<7> Jump to ISR
<8> Process ISR
<9> Pop contexts (r0-r3, r12,r14, r15 and xPSR)
<10> Return to the interrupted position

Here, the contents of <5> and <6>, and the target stack would be the same.
Therefore. CPU wants to omit the <5> and <6> processes to avoid the extra stack handling. If the next interrupt would come just before <5>, it would be possible.
This is the tail chaining. After all, the interrupt sequence would become the following.

<1> Detect Interrupt
<2> Push contexts (r0-r3, r12,r14, r15 and xPSR)
<3> Jump to ISR
<4> Process ISR
<7> Jump to ISR
<8> Process ISR
<9> Pop contexts (r0-r3, r12,r14, r15 and xPSR)
<10> Return to the interrupted position

As the results, 4 data push and 4 data pop (i.e. 8 cycles at the minimum) could be saved.
Can this help you?

Best regards,
Yasuhiko Koumoto.