can we delay read and write transactions(axi4) by providing delay in register slice?

Hello,

I want not to talk on hangout, because I will not support until you will succeed.
I can only give you hints.
I did my best by proposing an example which can work well in a certain environment
Now, I would like to finish the conversation.

By the way, if you have the AXI bridge, how about adding the following logics into the bridge?
As the wready can be generated independently with wvalid, any latches will not be needed.

assign wtimer_trigger = wvalid & wready_i;
assign wready = (wtimer == 5'h1) & wready_i;

always @(posedge clk) begin
if(reset)
   wtimer <= 5'h0;
else if(wtime != 5'h1)
   wtimer <= wrimer - 1;
else if(wtimer_trigger & (wtimer == 5'h0))
   wtimer <= 5'h10;
else if(wready)
   wtimer <= 5'h0;
end

Best regards,

Yasuhiko Koumoto.

Hello,

I want not to talk on hangout, because I will not support until you will succeed.
I can only give you hints.
I did my best by proposing an example which can work well in a certain environment
Now, I would like to finish the conversation.

By the way, if you have the AXI bridge, how about adding the following logics into the bridge?
As the wready can be generated independently with wvalid, any latches will not be needed.

assign wtimer_trigger = wvalid & wready_i;
assign wready = (wtimer == 5'h1) & wready_i;

always @(posedge clk) begin
if(reset)
   wtimer <= 5'h0;
else if(wtime != 5'h1)
   wtimer <= wrimer - 1;
else if(wtimer_trigger & (wtimer == 5'h0))
   wtimer <= 5'h10;
else if(wready)
   wtimer <= 5'h0;
end

Best regards,

Yasuhiko Koumoto.

Sir

Thank you so much for all the suggestions you have provided me.. You have really brought me this far. I have tried the write (with latches  ) it does not seem to work. Some last doubts to end the conversation. Please let me if your write channel is similar to mine and the test bench you have used to test it. I have tried the bridge suggestion as well. But that does not delay my data.

Regards

Hello,

I cannot judge whether your axi_mcb_w_channel logic would be correct or not.
It seems to have a lot of strange parts for me.
Honestry speaking, I wonder why my proposal for the bridge did not work.

I have tried the bridge suggestion as well. But that does not delay my data.

Is  your data modification done between the bridge and the slave?
My assumption is that it would be done between CPU and the bridge.

Best regards,

Yasuhiko Koumoto.

Yes sir I have made the modifications between bridge and the slave as I do not have access to the CPU part of the code. You can have a look at the attachment(axi_mcb_w_channel.v) to see where I have made the changes. Also I have attached axi bridge(axi_mcb.v). Sir, can you please tell me which particular simulator have you used.

I am working on the latch code sent by you.

Regards

Preet Kaur Walia

Hello,

I am afraid that you would insert the delay logic into the axi_mcb_{aw,w,b}_channel_0. It would be to very complex and difficult.

I recommend to put my logic on between the register slice and the axi_mcb_{aw,w,b}_channel_0.

Best regards,

Yasuhiko Koumoto.

Sir

I was trying this approach but the code you sent, in that only wvalid was masked. And in the diagram you have sent wready,wvalid and awraedy all are masked. So I am confused what all I need to mask.

assign wtimer_trigger = wvalid & wready_i;
assign wready = (wtimer == 5'h1) & wready_i;

always @(posedge clk) begin
if(reset)
   wtimer <= 5'h0;
else if(wtime != 5'h1)
   wtimer <= wrimer - 1;
else if(wtimer_trigger & (wtimer == 5'h0))
   wtimer <= 5'h10;
else if(wready)
   wtimer <= 5'h0;
end

Regards

Preet Kaur Walia

Hello,

my block diagram has the assumption that the axi_mcb_{aw,w,b}_channel_0 are original (i.e. no modification).

Please remove the wready generation logic from the axi_mcb_w_channel_0.

Best regards,

Yasuhiko Koumoto.

Hello,

let me give an additional comments.

To insert 15 cycle delay would be the easiest to do in the slave.

In a slave, we can easily control READY signal.

However, to do it outside of a slave would be a little difficult.

I had been looking at the outside solution.

Because the axi_mcb_{aw,w,b}_channel_0 would be a slave, I think that it would be enough to control only the wwreay signal.

However, you did the other signal (e.g. the awreay, etc.) controlling in the slave. It is not my intention.

Therefore, I proposed the bridge solution which the control would be put between master (or the register slice) and the slave under the condition which any modification would be added to he axi_mcb_{aw,w,b}_channel_0.

Best regards,

Yasuhiko Koumoto.

Yes I did that.

Hi

I have made a bridge between the register slice and write channel and added the delay code in that. That is I am delaying the wready signal in that. My doubt was that will delaying workif we only delay the wready signal. Others would not be required.

Regards

Preet

Hello,

don't you want to delay only the wdata for a slave, do you?

Do you want to add delay for the other signals?

Could you tell me the reason why the delaying won't work if we only delay the wready signal?

Best regards,

Yasuhiko Koumoto.

Sir

My write delay is working fine if I delay wready in my write channel. I have a doubt. If I am doing continous write and then I read continously, it is working fine(my each data word is getting delayed) but not in the case when I perform single read and single write. Is it that if I am not performing bursts(I do a single write and I read single data) the flow of data between different modules in AXI different to that to a single read and single write.

Regard

Preet Kaur Walia

Hello,

I think your code might support only the 4 burst case from the description below.

always @(posedge clk) begin
  if (w_complete_ns | reset) begin
    cnt <= {C_CNT_WIDTH{1'b1}};
  end else if (whandshake_i) begin
    cnt <= cnt - 1'b1;
  end
end
always @(posedge clk) begin
  if (reset | w_complete_ns) begin
    subburst_last <= 1'b0;
  end else if ((cnt == {{C_CNT_WIDTH-1{1'b0}},1'b1}) & whandshake_i) begin
    subburst_last <= 1'b1;
  end
end

Best regards,
Yasuhiko Koumoto.