We are running a survey to help us improve the experience for all of our members. If you see the survey appear, please take the time to tell us about your experience if you can.
Basically I want to provide delay of 15 clock cycles for writing and reading through axi4 bus .Is it possible?
Hello,
my block diagram has the assumption that the axi_mcb_{aw,w,b}_channel_0 are original (i.e. no modification).
Please remove the wready generation logic from the axi_mcb_w_channel_0.
Best regards,
Yasuhiko Koumoto.
Yes I did that.