Please note: We are aware of an issue affecting replies on the Arm Community forums, which may not be loading as expected.

We apologize for any inconvenience and appreciate your patience while we investigate and work to resolve the issue.

Thank you for your understanding.

  • State Accepted Answer
  • Locked Locked
  • Replies 67 replies
  • Subscribers 347 subscribers
  • Views 130067 views
  • Users 0 members are here
Options
Related
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

can we delay read and write transactions(axi4) by providing delay in register slice?

PREET

Basically I want to provide delay of 15 clock cycles  for writing and reading through axi4 bus .Is it possible?

Parents
  • 0 in reply to PREET

    Hello,


    I think your code might support only the 4 burst case from the description below.

    always @(posedge clk) begin
  if (w_complete_ns | reset) begin
    cnt <= {C_CNT_WIDTH{1'b1}};
  end else if (whandshake_i) begin
    cnt <= cnt - 1'b1;
  end
end
always @(posedge clk) begin
  if (reset | w_complete_ns) begin
    subburst_last <= 1'b0;
  end else if ((cnt == {{C_CNT_WIDTH-1{1'b0}},1'b1}) & whandshake_i) begin
    subburst_last <= 1'b1;
  end
end

    Best regards,
    Yasuhiko Koumoto.

Reply
  • 0 in reply to PREET

    Hello,


    I think your code might support only the 4 burst case from the description below.

    always @(posedge clk) begin
  if (w_complete_ns | reset) begin
    cnt <= {C_CNT_WIDTH{1'b1}};
  end else if (whandshake_i) begin
    cnt <= cnt - 1'b1;
  end
end
always @(posedge clk) begin
  if (reset | w_complete_ns) begin
    subburst_last <= 1'b0;
  end else if ((cnt == {{C_CNT_WIDTH-1{1'b0}},1'b1}) & whandshake_i) begin
    subburst_last <= 1'b1;
  end
end

    Best regards,
    Yasuhiko Koumoto.

Children
No data