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can we delay read and write transactions(axi4) by providing delay in register slice?

PREET over 9 years ago

Basically I want to provide delay of 15 clock cycles for writing and reading through axi4 bus .Is it possible?

Parents

0 Yasuhiko Koumoto over 9 years ago in reply to PREET

Hello,

I think your code might support only the 4 burst case from the description below.

always @(posedge clk) begin
  if (w_complete_ns | reset) begin
    cnt <= {C_CNT_WIDTH{1'b1}};
  end else if (whandshake_i) begin
    cnt <= cnt - 1'b1;
  end
end
always @(posedge clk) begin
  if (reset | w_complete_ns) begin
    subburst_last <= 1'b0;
  end else if ((cnt == {{C_CNT_WIDTH-1{1'b0}},1'b1}) & whandshake_i) begin
    subburst_last <= 1'b1;
  end
end

Best regards,
Yasuhiko Koumoto.

Reply

0 Yasuhiko Koumoto over 9 years ago in reply to PREET

Hello,

I think your code might support only the 4 burst case from the description below.

always @(posedge clk) begin
  if (w_complete_ns | reset) begin
    cnt <= {C_CNT_WIDTH{1'b1}};
  end else if (whandshake_i) begin
    cnt <= cnt - 1'b1;
  end
end
always @(posedge clk) begin
  if (reset | w_complete_ns) begin
    subburst_last <= 1'b0;
  end else if ((cnt == {{C_CNT_WIDTH-1{1'b0}},1'b1}) & whandshake_i) begin
    subburst_last <= 1'b1;
  end
end

Best regards,
Yasuhiko Koumoto.

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