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Basically I want to provide delay of 15 clock cycles for writing and reading through axi4 bus .Is it possible?
Sir
Thank you so much for all the suggestions you have provided me.. You have really brought me this far. I have tried the write (with latches ) it does not seem to work. Some last doubts to end the conversation. Please let me if your write channel is similar to mine and the test bench you have used to test it. I have tried the bridge suggestion as well. But that does not delay my data.
Regards
Hello,
I cannot judge whether your axi_mcb_w_channel logic would be correct or not.It seems to have a lot of strange parts for me.Honestry speaking, I wonder why my proposal for the bridge did not work.
I have tried the bridge suggestion as well. But that does not delay my data.
Is your data modification done between the bridge and the slave?My assumption is that it would be done between CPU and the bridge.
Best regards,
Yasuhiko Koumoto.
I am working on the latch code sent by you.
Preet Kaur Walia