can we delay read and write transactions(axi4) by providing delay in register slice?

Hi,

I cannot catch your intention.
Please let us know it.
Because latencies from "a read address valid" to "the corresponding read data responses" or from "a write address valid" to "the corresponding write response" would be unpredictable, is there any reason to add 15 cycle delay?
Do you want AT LEAST 15 cycle delay?
Do you design such a register slice by yourself?

Or do you want to by such a register slice?
I think if you want to do so, you can only do it.
What is the back ground of your question?

Best regards,
Yasuhiko Koumoto.

Hi preet729,

As "yasuhikokoumoto" says, we would need to know what is driving this requirement before anyone could suggest how to achieve this.

The interconnect logic between your master and your slave should be trying to pass information as quickly as possible, so it would be rare to see anything intentionally adding 15 cycles of delay.

Instead my first thought would be that if a master or a slave needs to delay any transfer completing on any channel, both the transfer source and the transfer destination have full control over the transfer timings using the AXI VALID and READY handshake signals.

So if for example your slave required at least 15 cycles between an AW channel transfer and the first W channel transfer, the slave can simply hold WREADY low for that amount of cycles.

Register Slices are there to break timing long paths, so adding up to a couple of clock cycles of latency depending on the design, but not 15.

You can add buffers in some ARM interconnects to data channels, but these will still try to pass the data from source to destination as soon as possible, so just adding one cycle of registering before making the data available to the destination device. Write data channel buffers can have something called "tidemark" levels which will stall the buffered write data until sufficient write data is buffered, or until the WLAST data transfer, but again not really guaranteeing any 15 cycle requirement.

So I would suggest that the component needing the 15 cycle delay should use the available READY and VALID handshake signals to implement the delay, unless you can explain why that isn't possible in your system, and what is driving this requirement.

JD

Thank you so much for your replies.

I am using memory controller block(Xilinx) and I need to delay the read and writes for 15 clock cycles so that I can modify the data being written to memory. Xilinx uses AXI bus . So I was thinking to delay the data when present in AXI bus. I have tried to delay the reading and writing but it has corrupted the data. I need to know where can I delay the data in AXI bus. And I have not made register slice myself . I was using the inbuilt AXI register slice to do so.

All suggestions are welcome

Regards

Preet

Also as said by @jd_ if i try to delay the data between aw and w channel. Then how will my system behave under burst mode. Because according to me in burst mode aw channel will be utilised once. As consecutive addresses will be calculated by the axi itself

Thank you so much for your replies.

I am using memory controller block(Xilinx) and I need to delay the read and writes for 15 clock cycles so that I can modify the data being written to memory. Xilinx uses AXI bus . So I was thinking to delay the data when present in AXI bus. I have tried to delay the reading and writing but it has corrupted the data. I need to know where can I delay the data in AXI bus. And I have not made register slice myself . I was using the inbuilt AXI register slice to do so.

Also as said by @jd_ if i try to delay the data between aw and w channel. Then how will my system behave under burst mode. Because according to me in burst mode aw channel will be utilised once. As consecutive addresses will be calculated by the axi itself.and therefore i wont be able provide delay to each data in burst mode.

All suggestions are welcome

Regards

Preet

Thank you so much for your replies.

I am using memory controller block(Xilinx) and I need to delay the read and writes for 15 clock cycles so that I can modify the data being written to memory. Xilinx uses AXI bus . So I was thinking to delay the data when present in AXI bus. I have tried to delay the reading and writing but it has corrupted the data. I need to know where can I delay the data in AXI bus. And I have not made register slice myself . I was using the inbuilt AXI register slice to do so.

Also as said by you if i try to delay the data between aw and w channel. Then how will my system behave under burst mode. Because according to me in burst mode aw channel will be utilised once. As consecutive addresses will be calculated by the axi itself.and therefore i wont be able provide delay to each data in burst mode.

All suggestions are welcome

Regards

Preet

Hi,

I think that you can make 15 cycle signal mask for both WVALID and WREADY.
Please see below.

Best regards,
Yasuhiko Koumoto.

I have understood from your suggestion that in the case of burst mode, when first address arrives then awvalid and awready will be high.  Then I can delay the wvalid and wready.  Will it work for burst mode.

Is that what you are trying to say?

Regards

Preet

Hi Preet,

of course it would be work for both single and burst modes.
However, my proposal is not a delay but a simple mask logic.
Please see below.

Best regards,
Yasuhiko Koumoto.

yasuyomurakami

Thank you for your suggestion. I will surely work on it.

Regards

Preet Kaur Walia

Sir,

Is the same circuit valid for the read channels as well?That is I can delay my read by delaying rready and rvalid signals.

Regards

Preet Kaur Walia

Hi Preet Kaur Walia,

in the read case, it would be a little complex because an interval time between "ARVALID & ARREADY" and "RVALID & RREADY" would be unpredictable.

You should make the timer trigger from the first read response.

Therefore, you should make a sequence controlling as

1. notice ARVALID & ARREADY

2. then RVALID & RREADY.

Best regards,

Yasuhiko Koumoto.

Sir

I am new to the AXI.

"You should make the timer trigger from the first read response."

Does this mean that I have to start the counter when the  done signal is high for the first read?

or

I should start the counter when,

count = arvalid & arready goes high..

then i should mask the rvalid and rready.

I am not able to understand the timing adjustments I have to make between these four signals.

And the difference between delaying procedure in read and write. I have been able to delay in write as per told by you. It worked

Regards

Preet

Hi Preet,
I mean the timing will be like below.

Also, both RVALID and RREADY should be masked by the mask signal.
Best regards,
Yasuhiko Koumoto.

Sir

i have tried it but not been able to make it.

I have done the following changes to delay my every read by 15 clock cycles.

assign count=arready&arvalid

if(count)

addr_done<=1

else if(rvalid & rready_new & rlast)

addr_done <=0

always@(posedge clk)

  begin

assign valid =((~rd_empty_d1 & ~rhandshake_d1) | rd_count_gt_2) & ~mask;

assign rready_new = rready & ~mask

  if (addr_done & rvalid & rready_new)

  begin

  case(state_delay)

  0: begin

  mask <=1;

  state_delay<=1;

  end

  1: begin

  mask <=1;

  state_delay<=2;

  end

  2: begin

  mask <=1;

  state_delay<=3;

  end

  3: begin

  mask <=1;

  state_delay<=4;

  end

  4: begin

  mask <=1;

  state_delay<=5;

  end

  5:begin

  mask <=1;

  state_delay<=6;

  end

  6: begin

  mask <=1;

  state_delay<=7;

  end

  7: begin

  mask <=1;

  state_delay<=8;

  end

  8: begin

  mask <=1;

  state_delay<=9;

  end

  9: begin

  mask <=1;

  state_delay<=10;

  end

  10: begin

  mask <=1;

  state_delay<=11;

  end

  11: begin

  mask <=1;

  state_delay<=12;

  end

  12: begin

  mask <=1;

  state_delay<=13;

  end

  13: begin

  mask <=1;

  state_delay<=14;

  end

  14: begin

  mask <=1;

  state_delay<=15;

  end

  15: begin

  mask <=1;

  rdata_changed<=rd_data + 1'b1; //for debugging

  state_delay<=16;

  end

  16:begin

  state_delay <= 0;

  mask <= 0;

  end

  endcase

  end

  end

I dont know where am I going wrong.

kindly help.

regards

Preet Kaur Walia