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can we delay read and write transactions(axi4) by providing delay in register slice?

PREET

Basically I want to provide delay of 15 clock cycles  for writing and reading through axi4 bus .Is it possible?

Parents
  • 0 in reply to PREET

    Hello,

    I cannot judge whether your axi_mcb_w_channel logic would be correct or not.
    It seems to have a lot of strange parts for me.
    Honestry speaking, I wonder why my proposal for the bridge did not work.

    I have tried the bridge suggestion as well. But that does not delay my data.

    Is  your data modification done between the bridge and the slave?
    My assumption is that it would be done between CPU and the bridge.

    Best regards,

    Yasuhiko Koumoto.

Reply
  • 0 in reply to PREET

    Hello,

    I cannot judge whether your axi_mcb_w_channel logic would be correct or not.
    It seems to have a lot of strange parts for me.
    Honestry speaking, I wonder why my proposal for the bridge did not work.

    I have tried the bridge suggestion as well. But that does not delay my data.

    Is  your data modification done between the bridge and the slave?
    My assumption is that it would be done between CPU and the bridge.

    Best regards,

    Yasuhiko Koumoto.

Children