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Basically I want to provide delay of 15 clock cycles for writing and reading through axi4 bus .Is it possible?
Thank you so much for your replies.
I am using memory controller block(Xilinx) and I need to delay the read and writes for 15 clock cycles so that I can modify the data being written to memory. Xilinx uses AXI bus . So I was thinking to delay the data when present in AXI bus. I have tried to delay the reading and writing but it has corrupted the data. I need to know where can I delay the data in AXI bus. And I have not made register slice myself . I was using the inbuilt AXI register slice to do so.
Also as said by you if i try to delay the data between aw and w channel. Then how will my system behave under burst mode. Because according to me in burst mode aw channel will be utilised once. As consecutive addresses will be calculated by the axi itself.and therefore i wont be able provide delay to each data in burst mode.
All suggestions are welcome
Regards
Preet
Hi,
I think that you can make 15 cycle signal mask for both WVALID and WREADY.Please see below.
Best regards,Yasuhiko Koumoto.
I have understood from your suggestion that in the case of burst mode, when first address arrives then awvalid and awready will be high. Then I can delay the wvalid and wready. Will it work for burst mode.
Is that what you are trying to say?
Hi Preet,
of course it would be work for both single and burst modes.However, my proposal is not a delay but a simple mask logic.Please see below.
yasuyomurakami
Thank you for your suggestion. I will surely work on it.
Preet Kaur Walia
Sir,
Is the same circuit valid for the read channels as well?That is I can delay my read by delaying rready and rvalid signals.
Hi Preet Kaur Walia,
in the read case, it would be a little complex because an interval time between "ARVALID & ARREADY" and "RVALID & RREADY" would be unpredictable.
You should make the timer trigger from the first read response.
Therefore, you should make a sequence controlling as
1. notice ARVALID & ARREADY
2. then RVALID & RREADY.
Best regards,
Yasuhiko Koumoto.
Sir
I am new to the AXI.
"You should make the timer trigger from the first read response."
Does this mean that I have to start the counter when the done signal is high for the first read?
or
I should start the counter when,
count = arvalid & arready goes high..
then i should mask the rvalid and rready.
I am not able to understand the timing adjustments I have to make between these four signals.
And the difference between delaying procedure in read and write. I have been able to delay in write as per told by you. It worked
Hi Preet,I mean the timing will be like below.
Also, both RVALID and RREADY should be masked by the mask signal.Best regards,Yasuhiko Koumoto.
i have tried it but not been able to make it.
I have done the following changes to delay my every read by 15 clock cycles.
assign count=arready&arvalid
if(count)
addr_done<=1
else if(rvalid & rready_new & rlast)
addr_done <=0
always@(posedge clk)
begin
assign valid =((~rd_empty_d1 & ~rhandshake_d1) | rd_count_gt_2) & ~mask;
assign rready_new = rready & ~mask
if (addr_done & rvalid & rready_new)
case(state_delay)
0: begin
mask <=1;
state_delay<=1;
end
1: begin
state_delay<=2;
2: begin
state_delay<=3;
3: begin
state_delay<=4;
4: begin
state_delay<=5;
5:begin
state_delay<=6;
6: begin
state_delay<=7;
7: begin
state_delay<=8;
8: begin
state_delay<=9;
9: begin
state_delay<=10;
10: begin
state_delay<=11;
11: begin
state_delay<=12;
12: begin
state_delay<=13;
13: begin
state_delay<=14;
14: begin
state_delay<=15;
15: begin
rdata_changed<=rd_data + 1'b1; //for debugging
state_delay<=16;
16:begin
state_delay <= 0;
mask <= 0;
endcase
I dont know where am I going wrong.
kindly help.
regards
Hello Preet Kaur Walia,
I think if (addr_done & rvalid & rready_new)would be wrong.The count start trigger should be the rising edge of "rvalid & rready".Therefore, the if statement should be replaced withif (addr_done & ~delayed_rvalid_rready & (rvalid_pre_mask & rready_pre_mask)).Here,awalways@(posedge clk) delayed_rvalid_rready <= rvalid_pre_mask & rready_pre_mask;
the statement
if (addr_done & ~delayed_rvalid_rready & (rvalid_pre_mask & rready_pre_mask))
How will this statement be responsible for checking the rising edge of the ready and valid signals.
Instead can i do this:
dealyed_rvalid_rready<=rvalid & rready;
always@(posedge clk or posedge count_in)
case(state)
if (count_in)
addr_done<=1;
state <= 1;
else
addr_done<=0;
state<=0;
if (rvalid_i & rready & rlast)
state <= 0;
always@(posedge clk or dealyed_rvalid_rready)
if ( addr_done & dealyed_rvalid_rready)
mask <=1;//provide delay as required by masking
state_delay<=0;
mask <=0;//stop the masking
I think your HDL description would generate the latch instead of the flip-flop. Is it OK?
Honestry speaking, I cannot understnd your HDL.
Is it working well?
No sir
Even after using the code below I am able to read the value written to previous address .
For example if i try to read 0x11111111 of my memory I read the value written to 0x11111110.I am using AXI bus to read.
assign count_in = arvalid and arready;
always@(posedge clk) //as suggested by you
delayed_rvalid_rready<=rvalid_i & rready;
always@(posedge clk )
if ( addr_done & ~dealyed_rvalid_rready & (rvalid_i & rready))
mask <=0;
1:begin
mask <=1;///so on for 15 cycle
15:
rdata_delayed<=rd_data ;
mask<=0;
first of all,
"For example if i try to read 0x11111111 of my memory I read the value written to 0x11111110.I am using AXI bus to read. "
would be impossible.
There is possibility to read the data before being written at 0x11111111.
This time, there is no consideration of such the read-after-write problem.
I think that there seems be some misunderstandings.
My proposal is to insert 15 cycle delay one time for one read or write transaction. It seems that you want to insert 15 cycle delay for each data cycle.
Please show us your timing diagram instead of HDL descriptions.
By the way, what is the number of outstandings by your master?
I only consider the number of outstandings is one.
Yes for each data cycle I want to add the delay for read and write transaction. For example in burst mode if I read 64 data words from memory. I want each of the read to be delayed by 15 clock cycles. As of the timing diagrams is considered I was following the timing provided by you to achieve the situation for read and write.
For write, the circuit diagram provided by you works for delaying each write(each datapath write and not one complete write transaction containing several data words written but delay to each dataword) by 15 clock cycles but the same is not happening for read(I am following your timing diagram.)
As I have understandood the outstandings by master(heer Mmeory controller block) are the number of transactions to and from the AXI bus can be any number. But maximum number can be 64 data words can be written in single burst. Each dataword width is 64 bits. First of all I want to know the timing diagram you have provided for read will not delay each read dataword? As of now I am assuming my HDL is wrong.
Preet Kaur