We are running a survey to help us improve the experience for all of our members. If you see the survey appear, please take the time to tell us about your experience if you can.
Basically I want to provide delay of 15 clock cycles for writing and reading through axi4 bus .Is it possible?
Sir
Yes for each data cycle I want to add the delay for read and write transaction. For example in burst mode if I read 64 data words from memory. I want each of the read to be delayed by 15 clock cycles. As of the timing diagrams is considered I was following the timing provided by you to achieve the situation for read and write.
For write, the circuit diagram provided by you works for delaying each write(each datapath write and not one complete write transaction containing several data words written but delay to each dataword) by 15 clock cycles but the same is not happening for read(I am following your timing diagram.)
As I have understandood the outstandings by master(heer Mmeory controller block) are the number of transactions to and from the AXI bus can be any number. But maximum number can be 64 data words can be written in single burst. Each dataword width is 64 bits. First of all I want to know the timing diagram you have provided for read will not delay each read dataword? As of now I am assuming my HDL is wrong.
Regards
Preet Kaur