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How many cycles requires the instruction QBNE?

QBNE (Quick branch not equal)

Using the PRU in the Beaglebone black (AM335x 1GHz ARM® Cortex-A8) I am asking how many cycles requires the instruction QBNE?

qbeq myLabel, r1, 0

I suppose two if the comparison is false: one is for compare and one is for the jump.

Instead, one, just the compare.

Thanks,

Br

Parents Reply Children
  • if (r1 != 0 ) jump

    Anyway, how many cycles does it require?

  • The PRU isn't an ARM core - it's a TI developed custom RISC microcontroller. You may get more answers asking on the TI developer forums.

    HTH,
    Pete

  • I logged out and didn't notice your reply.

    You asked for QBNE in your question but used qbeq in your example.

    I also don't know the exact number of cycles these instructions take. I got curious in your question because I also would like to know the answer. A couple of years back, I already searched for a document tabulating the number of cycles each PRU instructions would take but I have not found it. The only information that I know is probably just similar to what you have: most instructions execute in single cycle except when accessing external memory.

    Like Pete's reply I recommend you try if you can obtain the answer from TI's E2E Community.

  • Hello,

    I got this answer from TI:

    "You can view the Cortex-A8 documentation in the ARM website download area: infocenter.arm.com/.../index.jsp Cortex-A8 revision for AM335X is r3p2.

    Best Regards

    Biser"

    Anyway, I have found the answer with a small test with an oscilloscope:

      MOV r0, 20000  // store the length of the delay of status 1 in REG0
    DELAYON:
      SUB r0, r0, 1   // Decrement REG0 by 1, delay register
      QBNE DELAYON, r0, 0   // Loop to DELAYON, unless REG0=0

    From the experimental test the DelayON needs 200000ns (200us) for execute the 20000 loop.

    So, with 5ns per cycle, QBNE requires just 1 cycle for instruction.


    Br,
    Alex

  • The documents we can get from ARM Infocenter relate only to the main microprocessor unit of the AM335x. The technical documents for the PRU-ICSS should come from TI.

    From the experimental test the DelayON needs 200000ns (200us) for execute the 20000 loop.

    So, with 5ns per cycle, QBNE requires just 1 cycle for instruction.

    More likely this is correct. (Perhaps) the Quick Branch instructions are called Quick Branch, rather than just Branch, because they execute in just 1 cycle.