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How many cycles requires the instruction QBNE?

Alex

QBNE (Quick branch not equal)

Using the PRU in the Beaglebone black (AM335x 1GHz ARM® Cortex-A8) I am asking how many cycles requires the instruction QBNE?

qbeq myLabel, r1, 0

I suppose two if the comparison is false: one is for compare and one is for the jump.

Instead, one, just the compare.

Thanks,

Br

Parents
  • +1 in reply to Alex

    Hello,

    I got this answer from TI:

    "You can view the Cortex-A8 documentation in the ARM website download area: infocenter.arm.com/.../index.jsp Cortex-A8 revision for AM335X is r3p2.

    Best Regards

    Biser"

    Anyway, I have found the answer with a small test with an oscilloscope:

      MOV r0, 20000  // store the length of the delay of status 1 in REG0
    DELAYON:
      SUB r0, r0, 1   // Decrement REG0 by 1, delay register
      QBNE DELAYON, r0, 0   // Loop to DELAYON, unless REG0=0

    From the experimental test the DelayON needs 200000ns (200us) for execute the 20000 loop.

    So, with 5ns per cycle, QBNE requires just 1 cycle for instruction.


    Br,
    Alex

Reply
  • +1 in reply to Alex

    Hello,

    I got this answer from TI:

    "You can view the Cortex-A8 documentation in the ARM website download area: infocenter.arm.com/.../index.jsp Cortex-A8 revision for AM335X is r3p2.

    Best Regards

    Biser"

    Anyway, I have found the answer with a small test with an oscilloscope:

      MOV r0, 20000  // store the length of the delay of status 1 in REG0
    DELAYON:
      SUB r0, r0, 1   // Decrement REG0 by 1, delay register
      QBNE DELAYON, r0, 0   // Loop to DELAYON, unless REG0=0

    From the experimental test the DelayON needs 200000ns (200us) for execute the 20000 loop.

    So, with 5ns per cycle, QBNE requires just 1 cycle for instruction.


    Br,
    Alex

Children
  • 0 in reply to Alex

    The documents we can get from ARM Infocenter relate only to the main microprocessor unit of the AM335x. The technical documents for the PRU-ICSS should come from TI.

    From the experimental test the DelayON needs 200000ns (200us) for execute the 20000 loop.

    So, with 5ns per cycle, QBNE requires just 1 cycle for instruction.

    More likely this is correct. (Perhaps) the Quick Branch instructions are called Quick Branch, rather than just Branch, because they execute in just 1 cycle.