Dual A53 cluster, MMU configuration

Majid Ghameshlu said:

is there any possibility that the MMU configuration of core 1 is only done by core 0?

The MMU is configured through a combination of system register settings and translation tables held in memory.

System registers are only accessible from the owning core.  Meaning, only core 0 can access core's 0 system registers, only core 1 can access core 1's system registers.  So that part of the MMU set up, initialising the registers, can't be done by core 0 on behalf of core 1.  Core 0 could set up the tables in memory that core 1 will later use.

Based on the questions, I think you're trying to ensure isolation of the workload on core 0 from that on core 1.  If that's right, there are some other approaches you could investigate.  For example, TrustZone and Virtualisation can both be used to provide isolation, either separately or in combination.

Majid Ghameshlu said:

is there any possibility that the MMU configuration of core 1 is only done by core 0?

The MMU is configured through a combination of system register settings and translation tables held in memory.

System registers are only accessible from the owning core.  Meaning, only core 0 can access core's 0 system registers, only core 1 can access core 1's system registers.  So that part of the MMU set up, initialising the registers, can't be done by core 0 on behalf of core 1.  Core 0 could set up the tables in memory that core 1 will later use.

Based on the questions, I think you're trying to ensure isolation of the workload on core 0 from that on core 1.  If that's right, there are some other approaches you could investigate.  For example, TrustZone and Virtualisation can both be used to provide isolation, either separately or in combination.

Majid Ghameshlu said:

would it be OK, if we now assume a hypervisor on core 1 which takes care of e.g. MMU configuration and the unsecure application runs under the control of this hypervisor?

In principle, yes - although how practical it is depends heavily on the use case.  

Majid Ghameshlu said:

the unsecure application needs to access a slave on the interconnect (e.g. Ethernet IP).
what happens if a hacked SW on core 1 tries to generate lots of accesses to this module and therefore the performance of core 0 is affected?
Since both cores share the L2 Cache and the AXI master interface for the connection to the interconnect.
is it possible to restrict band width of core 1 inside the dual core subsystem? are there any arbitration between these two cores which can be configured by the user?

What you're describing is availability or quality of service.  There are different ways to approach this, again depending on what you want to be able to guarantee. For example, you could monitor performance and apply throttling. or you can have memory system level QoS features (example).  More recent Armv8 and Armv9 can support MPAM, which is another option.