Hello,we have a A53 cluster with two cores, core 0 and core 1.is there any possibility that the MMU configuration of core 1 is only done by core 0?since on core 1 a non secure application is running.
after core 0 has done the MMU setup for Core 1, it should be forbidden for core 1 to change this its MMU configuration
thanks
Majid
Hallo Martin,
thanks for the fast reply,
would it be OK, if we now assume a hypervisor on core 1 which takes care of e.g. MMU configuration and the unsecure application runs under the control of this hypervisor?
another question:
the unsecure application needs to access a slave on the interconnect (e.g. Ethernet IP).what happens if a hacked SW on core 1 tries to generate lots of accesses to this module and therefore the performance of core 0 is affected?Since both cores share the L2 Cache and the AXI master interface for the connection to the interconnect.is it possible to restrict band width of core 1 inside the dual core subsystem? are there any arbitration between these two cores which can be configured by the user?
Thanks
Majid Ghameshlu said:would it be OK, if we now assume a hypervisor on core 1 which takes care of e.g. MMU configuration and the unsecure application runs under the control of this hypervisor?
In principle, yes - although how practical it is depends heavily on the use case.
Majid Ghameshlu said:the unsecure application needs to access a slave on the interconnect (e.g. Ethernet IP).what happens if a hacked SW on core 1 tries to generate lots of accesses to this module and therefore the performance of core 0 is affected?Since both cores share the L2 Cache and the AXI master interface for the connection to the interconnect.is it possible to restrict band width of core 1 inside the dual core subsystem? are there any arbitration between these two cores which can be configured by the user?
What you're describing is availability or quality of service. There are different ways to approach this, again depending on what you want to be able to guarantee. For example, you could monitor performance and apply throttling. or you can have memory system level QoS features (example). More recent Armv8 and Armv9 can support MPAM, which is another option.
Hallo Martin,we want to guarantee that core 1 has at maximum 20% load of AXI master interface of A53 MPCORE and the core 0 80%.is there any QoS features inside the A53 MPCORE?