Hello all,
I am trying to find resources to turn off prefetchers (l1 and l2) for cortex a72.
So far I have been trying to understand https://developer.arm.com/documentation/100095/0001/level-2-memory-system/l2-cache-prefetcher But I am not sure how to write into these registers
I am familiar with intel and the instructions (read: wrmsr and rdmsr ) to read into model-specific registers but I couldn't find any for arm.
Is there any resource that can help me write into these registers and also mention the caveats [privileges required etc ] for writing ?
Thanks & Regards
Anilava
Disable L1 data cache and unified L2 cache . Disable the load-store hardware prefetcher. This applies only to revision <= r0p3 of Cortex A72.
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