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On Cortex-M7, can speculative access bring accessed data to D cache?

Pavel A

Asking this to better understand how to manage cache consistency on I/O buffer for DMA read.

Is it possible that in between of cache invalidation on the buffer and end of DMA read, a speculative data access brings incomplete data to the cache?

When the cache on DMA read buffer (device to CPU) should be invalidated: before starting DMA, or after the DMA ends?

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  • 0 in reply to Pavel A

    (answering to myself)

    The definitive answer can be found in CM7 TRM for r1p2 (2018) , section 5.2

    "Speculative data reads can be initiated to any Normal, read/write, or read-only memory
    address. In some rare cases, this can occur regardless of whether there is any instruction
    that causes the data read."

    "Speculative cache linefills are never made to Non-cacheable memory addresses"

    My conclusion from this: if DMA read buffer is defined non-cacheable, speculative read can occur, but it won't pollute D-cache.

    Speculative linefills from non-cacheable memory are forbidden.

    So, defining a DMA buffer non-cacheable, or non-normal (SO, device) should prevent D-cache pollution.

    "Cache maintenance" cannot avoid speculative linefills during DMA read If the buffer is normal cacheable memory.

    (What is said there about TCM memories is not relevant because TCM memories are normally not used with DMA)

    Comments are welcome.

Reply
  • 0 in reply to Pavel A

    (answering to myself)

    The definitive answer can be found in CM7 TRM for r1p2 (2018) , section 5.2

    "Speculative data reads can be initiated to any Normal, read/write, or read-only memory
    address. In some rare cases, this can occur regardless of whether there is any instruction
    that causes the data read."

    "Speculative cache linefills are never made to Non-cacheable memory addresses"

    My conclusion from this: if DMA read buffer is defined non-cacheable, speculative read can occur, but it won't pollute D-cache.

    Speculative linefills from non-cacheable memory are forbidden.

    So, defining a DMA buffer non-cacheable, or non-normal (SO, device) should prevent D-cache pollution.

    "Cache maintenance" cannot avoid speculative linefills during DMA read If the buffer is normal cacheable memory.

    (What is said there about TCM memories is not relevant because TCM memories are normally not used with DMA)

    Comments are welcome.

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