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On Cortex-M7, can speculative access bring accessed data to D cache?

Pavel A

Asking this to better understand how to manage cache consistency on I/O buffer for DMA read.

Is it possible that in between of cache invalidation on the buffer and end of DMA read, a speculative data access brings incomplete data to the cache?

When the cache on DMA read buffer (device to CPU) should be invalidated: before starting DMA, or after the DMA ends?

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    For Cortex-M7, it is possible depending on your software memory access pattern. 

    A specualtive data access could happen during the DMA operation. In some cases, the specualtive data access might be made to the DMA buffer, for example, accessing adjacent cacheable memory.

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    For Cortex-M7, it is possible depending on your software memory access pattern. 

    A specualtive data access could happen during the DMA operation. In some cases, the specualtive data access might be made to the DMA buffer, for example, accessing adjacent cacheable memory.

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