On Cortex-M7, can speculative access bring accessed data to D cache?

Asking this to better understand how to manage cache consistency on I/O buffer for DMA read.

Is it possible that in between of cache invalidation on the buffer and end of DMA read, a speculative data access brings incomplete data to the cache?

When the cache on DMA read buffer (device to CPU) should be invalidated: before starting DMA, or after the DMA ends?