Cortex A9 MPCore Interrupts

I'm writing a bare metal code for handling interrupts on an iMX6Quad (NXP) so A9 MPCore core. I'm having difficultly having the core (just using core1) respond to an interrupt. I chose the local timer for simplicity. In the iMX6, it is vector 29. The pertinent code is shown in the file Interrupts.txt. After the code runs for awhile, I halted it to see what was going on. What was supposed to happen was the code would halt at a breakpoint set at the first instruction in irq_isr (which didn't happen). Most of the affected registers are shown in the file Interrupt 1.png. On the left you can see that EVENT_FLAG is set, as is the interrupt enable. In the GICD_CTLR reg, both secure and non-secure enables are set. In GICD_GROUPR0, vector 29 is set to group 1 (non-secure). The ISENABLER0 reg shows vector 29 is enabled. Vector 29 is "hard-targeted" to core 1 since it is a PPI. GICD_PRIORITY29 is set to 0xA0 (see Interrupts 2). The GICC_CTLR shows both secure and non-secure interrupts being forwarded. The PMR reg shows a priority of 0xFF which is the lowest priority. The IAR reg shows vector 29; and the RPR reg shows that it picked up the new priority of 0xA0. The function set_vbar WAS called in the boot up code. The "I" bit in the CPSR is set low to enable the IRQ exception.

// This is the actual hardware exception table, the address of which is loaded
// into the VBAR. This section must be aligned on a 4-byte boundary (VBAR)
vector_tbl
     ldr pc, =__boot
     ldr pc, =undef_isr
     ldr pc, =svc_isr
     ldr pc, =prefetch_isr
     ldr pc, =abort_isr
     nop                     // reserved
     ldr pc, =irq_isr
     ldr pc, =fiq_isr


/*******************************************************************************
 * Set the location of the hardware vector table into the VBAR reg
 * On entry, r0 holds the location
 ******************************************************************************/
set_vbar
     ldr r0, =vector_tbl
     mcr p15, 0, r0, c12, c0, 0      //write VBAR register

     // SCTLR bit V - location of exception vectors -> 0x00000000-0x0000001C
     mrc p15, 0, r0, c1, c0, 0       //read SCTLR
     bic r0, r0, #0x2000             //clear V bit
     mcr p15, 0, r0, c1, c0, 0       //write SCTLR

     bx lr                           //return


/*******************************************************************************
 * Handle IRQ exception
 ******************************************************************************/
irq_isr
     // Save registers
     push   {r0-r12, lr}
     
     // Call the IRQ Exception handler
     ldr    r0, =irq_hnlr   //make sure bit0 is 0
     blx    r0
     
     // Return to normal program flow
     pop    {r0-r12, lr}
     subs   pc, lr, #4

What I expect should happen is that at this point, execution should jump to the IRQ exception, which would start execution at irq_isr, but this never happens. I'm sure I'm overlooking something, but I don't know what it is? Can anyone help?