// This is the actual hardware exception table, the address of which is loaded
// into the VBAR. This section must be aligned on a 4-byte boundary (VBAR)
vector_tbl
     ldr pc, =__boot
     ldr pc, =undef_isr
     ldr pc, =svc_isr
     ldr pc, =prefetch_isr
     ldr pc, =abort_isr
     nop                     // reserved
     ldr pc, =irq_isr
     ldr pc, =fiq_isr


/*******************************************************************************
 * Set the location of the hardware vector table into the VBAR reg
 * On entry, r0 holds the location
 ******************************************************************************/
set_vbar
     ldr r0, =vector_tbl
     mcr p15, 0, r0, c12, c0, 0      //write VBAR register

     // SCTLR bit V - location of exception vectors -> 0x00000000-0x0000001C
     mrc p15, 0, r0, c1, c0, 0       //read SCTLR
     bic r0, r0, #0x2000             //clear V bit
     mcr p15, 0, r0, c1, c0, 0       //write SCTLR

     bx lr                           //return


/*******************************************************************************
 * Handle IRQ exception
 ******************************************************************************/
irq_isr
     // Save registers
     push   {r0-r12, lr}
     
     // Call the IRQ Exception handler
     ldr    r0, =irq_hnlr   //make sure bit0 is 0
     blx    r0
     
     // Return to normal program flow
     pop    {r0-r12, lr}
     subs   pc, lr, #4