507                              ASM_CODE_SECTION(vector_rom)
  508                           
  509                           // This is the actual hardware exception
                                 table, the address of which is loaded
  510                           // into the VBAR. This section must be aligned
                                 on a 4-byte boundary (VBAR)
  511                           _vector_tbl
  512    00000000 18F09FE5           ldr pc, reset_addr
  513    00000004 18F09FE5           ldr pc, undefined_addr
  514    00000008 18F09FE5           ldr pc, svc_addr
  515    0000000C 18F09FE5           ldr pc, prefetch_addr
  516    00000010 18F09FE5           ldr pc, abort_addr
  517    00000014 00F020E3           nop                 /* reserved */
  518    00000018 18F09FE5           ldr pc, irq_addr
  519    0000001C 18F09FE5           ldr pc, fiq_addr
  520                           
  521                           ASM_LABEL(_vector_addr)
  522    00000020 ........      ASM_LABEL_CONST32(reset_addr, __boot)
  523    00000024 ........      ASM_LABEL_CONST32(undefined_addr, undefined_handler
  524    00000028 ........      ASM_LABEL_CONST32(svc_addr, svc_handler)
  525    0000002C ........      ASM_LABEL_CONST32(prefetch_addr, prefetch_handler
  526    00000030 ........      ASM_LABEL_CONST32(abort_addr, abort_handler)
  527    00000034 00000000      ASM_LABEL_CONST32(resvd_addr, 0)
  528    00000038 ........      ASM_LABEL_CONST32(irq_addr, irq_handler)
  529    0000003C ........      ASM_LABEL_CONST32(fiq_addr, fiq_handler)


/*******************************************************************************
 * Set the location of the hardware vector table into the VBAR reg
 * On entry, r0 holds the location
 ******************************************************************************/
set_vbar
     ldr r0, =vector_tbl
     mcr p15, 0, r0, c12, c0, 0      //write VBAR register

     // SCTLR bit V - location of exception vectors -> 0x00000000-0x0000001C
     mrc p15, 0, r0, c1, c0, 0       //read SCTLR
     bic r0, r0, #0x2000             //clear V bit
     mcr p15, 0, r0, c1, c0, 0       //write SCTLR

     bx lr                           //return


/*******************************************************************************
 * Handle IRQ exception
 ******************************************************************************/
irq_isr
     // Save registers
     push   {r0-r12, lr}
     
     // Call the IRQ Exception handler
     ldr    r0, =irq_hnlr   //make sure bit0 is 0
     blx    r0
     
     // Return to normal program flow
     pop    {r0-r12, lr}
     subs   pc, lr, #4