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how to understand multi-copy atomicity and who is in charge to maintain this property

summer123

hi,

the concept of multi-copy atomicity always troubles me , so could you kindly help to answer the three questions:

#1 how to understand multi-copy atomicity ?

#2 who is in charge to maintain multi-copy atomicity in soc system ,interconnect or other components ,like cpu?

#3 how to maintain this property ?

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  • 0

    In arm arm, it says that

    >#1 how to understand multi-copy atomicity ?

    Multi-copy atomicity

    In a multiprocessing system, writes to a memory location are multi-copy atomic if the following conditions are both
    true:
    • All writes to the same location are serialized, meaning they are observed in the same order by all observers,
    although some observers might not observe all of the writes.
    • A read of a location does not return the value of a write until all observers observe that write.

    Writes that are not coherent are not multi-copy atomic.

     

    For example,

    CPU0 writes A location, a=1;

    CPU1 writes A location, a=2;

    At a given time, it is not possible that

    CPU3 reads A=1 and CPU4 reads A=2.

    >#2 who is in charge to maintain multi-copy atomicity in soc system ,interconnect or other components ,like cpu?

    It requires processor, interconnect (e.g. cache coherent interconnect) working together.

    >#3 how to maintain this property ?

    Firstly, it is the responsibility of SoC designer to ensure that their system supports multi-copy atomic, and then software should make sure that the location is coherent (e.g. in shared cacheable memory region and non cacheable memory region).

     

Reply
  • 0

    In arm arm, it says that

    >#1 how to understand multi-copy atomicity ?

    Multi-copy atomicity

    In a multiprocessing system, writes to a memory location are multi-copy atomic if the following conditions are both
    true:
    • All writes to the same location are serialized, meaning they are observed in the same order by all observers,
    although some observers might not observe all of the writes.
    • A read of a location does not return the value of a write until all observers observe that write.

    Writes that are not coherent are not multi-copy atomic.

     

    For example,

    CPU0 writes A location, a=1;

    CPU1 writes A location, a=2;

    At a given time, it is not possible that

    CPU3 reads A=1 and CPU4 reads A=2.

    >#2 who is in charge to maintain multi-copy atomicity in soc system ,interconnect or other components ,like cpu?

    It requires processor, interconnect (e.g. cache coherent interconnect) working together.

    >#3 how to maintain this property ?

    Firstly, it is the responsibility of SoC designer to ensure that their system supports multi-copy atomic, and then software should make sure that the location is coherent (e.g. in shared cacheable memory region and non cacheable memory region).

     

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