hi,
the concept of multi-copy atomicity always troubles me , so could you kindly help to answer the three questions:
#1 how to understand multi-copy atomicity ?
#2 who is in charge to maintain multi-copy atomicity in soc system ,interconnect or other components ,like cpu?
#3 how to maintain this property ?
Did you read this: www.cl.cam.ac.uk/.../armv8-mca-draft.pdfSeems to be a good introduction.
In arm arm, it says that
>#1 how to understand multi-copy atomicity ?
Multi-copy atomicity
In a multiprocessing system, writes to a memory location are multi-copy atomic if the following conditions are bothtrue:• All writes to the same location are serialized, meaning they are observed in the same order by all observers,although some observers might not observe all of the writes.• A read of a location does not return the value of a write until all observers observe that write.
Writes that are not coherent are not multi-copy atomic.
For example,
CPU0 writes A location, a=1;
CPU1 writes A location, a=2;
At a given time, it is not possible that
CPU3 reads A=1 and CPU4 reads A=2.
>#2 who is in charge to maintain multi-copy atomicity in soc system ,interconnect or other components ,like cpu?
It requires processor, interconnect (e.g. cache coherent interconnect) working together.
>#3 how to maintain this property ?
Firstly, it is the responsibility of SoC designer to ensure that their system supports multi-copy atomic, and then software should make sure that the location is coherent (e.g. in shared cacheable memory region and non cacheable memory region).
hi, zenon
thanks a lot for you reply,
for the reply #1, if cpu3 read is between CPU0 W and CPU1 W , and CPU4 read is after CPU1 W,
at the time after cpu4 read, i think CPU3 reads A=1 and CPU4 reads A=2. as below shown:
could you help to confirm ?
for the reply #2, multi-copy atomicity is supported both for AXI and ACE, so if AXI is used , does NIC-400 support it?
for the reply #3 , i think multi-copy atomicity has no relationship with cache coherent, so what do you mean of "software should make sure that the location is coherent "?
and how does software make sure that the location is coherent?
look forward to get you reply, thanks
hi, bastian,
thanks , i will read it.
> at the time after cpu4 read, i think CPU3 reads A=1 and CPU4 reads A=2. as below shown
Yes, it is possible.
It is allowed since CPU 3 read and CPU 4 read is not at the same time.
>does NIC-400 support it?
Yes,NIC-400 supports multi-copy atomic
>for the reply #3
In general, software should set the memory attribute as Shared, Inner/outter Normal WriteBack WriteAllocate Cacheable.
thanks very much for you reply, but it still come over me about question#3
if the location is shared and coherent, base on coherent standard, the cache line is unique or shareable, so each master could get the same value from the cache copy when hit.
and when miss, only SCU or CCI main port will visit the memory, so there is no multi-copy atomic problem
could you help to confirm what i understand？
if my understanding is no problem, so only masters with no coherent condition need to consider multi-copy atomic problem, is it right?