hi,
the concept of multi-copy atomicity always troubles me , so could you kindly help to answer the three questions:
#1 how to understand multi-copy atomicity ?
#2 who is in charge to maintain multi-copy atomicity in soc system ,interconnect or other components ,like cpu?
#3 how to maintain this property ?
hi, zenon
thanks very much for you reply, but it still come over me about question#3
if the location is shared and coherent, base on coherent standard, the cache line is unique or shareable, so each master could get the same value from the cache copy when hit.
and when miss, only SCU or CCI main port will visit the memory, so there is no multi-copy atomic problem
could you help to confirm what i understand？
if my understanding is no problem, so only masters with no coherent condition need to consider multi-copy atomic problem, is it right?
look forward to get you reply, thanks