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why does LDR takes two cycle to be executed

Hello everyone,

I am currently working on a cortex-M0 microprocessor(LPC1114). I have looked through all the possible instruction descriptions but I did not find anyone of them explaining why some instructions takes two cycle to execute.

For example, ANDS, MOVS takes only one cycle to execute. but why do we need two cycles to execute LDR? and STR?

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Joseph Yiu over 4 years ago in reply to d.ry +2

Hi, In Cortex-M3 and Cortex-M4, the LDR for single load takes two cycles. This is documented in http://infocenter.arm.com/help/topic/com.arm.doc.100166_0001_00_en/ric1417175925887.html The Cortex...
Joseph Yiu over 5 years ago in reply to Haohao +1 verified

Cortex-M0 is based on a simple 3 stage pipeline design: Fetch, decode, execute. The data access starts at execution stage - due to pipeline nature of AHB bus protocol, the data transfer is 1 cycle after...
Joseph Yiu over 3 years ago in reply to d.ry +1

For bus system design, Arm have this book available: https://www.arm.com/resources/education/books/soc-reference-book This only cover AHB and APB, but not AXI (too much information for a single book...

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0 42Bastian Schick over 5 years ago in reply to Haohao

Sorry, I have no idea about pipeline etc.
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0 42Bastian Schick over 5 years ago in reply to Haohao

Sorry, I have no idea about pipeline etc.
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