why does LDR takes two cycle to be executed

http://infocenter.arm.com/help/topic/com.arm.doc.100166_0001_00_en/ric1417175925887.html

The Cortex-M3 and Cortex-M4 are three stage pipeline with simple fetch-decode-execute arrangement.

The LDR's address cycle is the first cycle of execute, and the read data is available in the next cycle, hence the single LDR takes two cycles. For multiple load store instructions or back to back load we can detect the next operation is also a data memory access and generate the address for it while the pipeline is waiting for the first data. Therefore if the multiple load reads N data, it takes N+1 cycles.

For stores, the address is also output in the execute stage, but the processor do not need to wait until the write is completed in the next cycle because there is a write buffer at the bus interface. Hence stores only take one cycle.

The address generation unit use a combinatorial path to handle the address generation (Rn+Rm) or (Rn+offset) and output to the bus immediately without registering it. As a result it doesn't take an extra cycle, but it means the timing constraint on the bus interface is tight.

Please note if you measure timing with DWT cycle counter with single step, the enable and disabling of that counter is not gurrantee to match the execution cycles at halting and unhalting.

regards,

Joseph

http://infocenter.arm.com/help/topic/com.arm.doc.100166_0001_00_en/ric1417175925887.html

The Cortex-M3 and Cortex-M4 are three stage pipeline with simple fetch-decode-execute arrangement.

The LDR's address cycle is the first cycle of execute, and the read data is available in the next cycle, hence the single LDR takes two cycles. For multiple load store instructions or back to back load we can detect the next operation is also a data memory access and generate the address for it while the pipeline is waiting for the first data. Therefore if the multiple load reads N data, it takes N+1 cycles.

For stores, the address is also output in the execute stage, but the processor do not need to wait until the write is completed in the next cycle because there is a write buffer at the bus interface. Hence stores only take one cycle.

The address generation unit use a combinatorial path to handle the address generation (Rn+Rm) or (Rn+offset) and output to the bus immediately without registering it. As a result it doesn't take an extra cycle, but it means the timing constraint on the bus interface is tight.

Please note if you measure timing with DWT cycle counter with single step, the enable and disabling of that counter is not gurrantee to match the execution cycles at halting and unhalting.

regards,

Joseph

Joseph Yiu : is there a new /recent book which covers ARM v7 and all cortex'es M and the ARM bus details to the great detail..? I mean not multiple ARM manuals, but a book consolidating it in great detail.

https://www.arm.com/resources/education/books/soc-reference-book

This only cover AHB and APB, but not AXI (too much information for a single book to cover all).

regards,

Joseph