Hello everyone,
I am currently working on a cortex-M0 microprocessor(LPC1114). I have looked through all the possible instruction descriptions but I did not find anyone of them explaining why some instructions takes two cycle to execute.
For example, ANDS, MOVS takes only one cycle to execute. but why do we need two cycles to execute LDR? and STR?
Hello Joseph Yiu,
But what about LDR on CM4 (and I think it's same on CM3) : why does it take 2 cycles - by the CM4 tech manual, and the hardware cycle counter as I checked - even for this type of LDR example :
LDR r0, [r1, r2] ?
Please correct me, but doesn't it need extra cycle to calculate r1 + r2? Looking at the older ARM7TDMI spec, LDR is a 3 cycle, one spent to calculate the destination address. And I tried reasoning how the extra cycle could be hidden, but I cannot really find 100% explanation (one thing I thought, CM3, CM4 are Harvard, perhaps memory write and instruction fetch can happen at same time..but , there is still cycle needed to update the register with memory contents before next instruction?)
For case of STR taking only one cycle on CM4, the manual says :"STR Rx,[Ry,#imm] is always one cycle. This is because the address generation is performed in the initial cycle, and the data store is performed at the same time as the next instruction is executing."
So the espec is "cheating" somewhat, as there is last cycle but it's happening as the next one is executing at least.
There is nothing more detailed in CM4 manual about how LDR is implemented however.
Clarification would be very much appreciated - about how / why LDR only is takes 2 cycles here (Ignoring case when its to to /from PC, which takes longer).
Hi,
In Cortex-M3 and Cortex-M4, the LDR for single load takes two cycles. This is documented in
http://infocenter.arm.com/help/topic/com.arm.doc.100166_0001_00_en/ric1417175925887.html
The Cortex-M3 and Cortex-M4 are three stage pipeline with simple fetch-decode-execute arrangement.
The LDR's address cycle is the first cycle of execute, and the read data is available in the next cycle, hence the single LDR takes two cycles. For multiple load store instructions or back to back load we can detect the next operation is also a data memory access and generate the address for it while the pipeline is waiting for the first data. Therefore if the multiple load reads N data, it takes N+1 cycles.
For stores, the address is also output in the execute stage, but the processor do not need to wait until the write is completed in the next cycle because there is a write buffer at the bus interface. Hence stores only take one cycle.
The address generation unit use a combinatorial path to handle the address generation (Rn+Rm) or (Rn+offset) and output to the bus immediately without registering it. As a result it doesn't take an extra cycle, but it means the timing constraint on the bus interface is tight.
Please note if you measure timing with DWT cycle counter with single step, the enable and disabling of that counter is not gurrantee to match the execution cycles at halting and unhalting.
regards,
Joseph
Reading this excellent detailed answer only now ... After my first detailed ARM course.
Joseph Yiu : is there a new /recent book which covers ARM v7 and all cortex'es M and the ARM bus details to the great detail..? I mean not multiple ARM manuals, but a book consolidating it in great detail.
For bus system design, Arm have this book available:
https://www.arm.com/resources/education/books/soc-reference-book
This only cover AHB and APB, but not AXI (too much information for a single book to cover all).