Some question about Arm Embedded Evaluation Kit

1.  Dedicated SRAM is a memory mode where tensor arena & model live in DRAM. SRAM is only used as a cache. Now, U55 is not designed to use DRAM as it's memory interface will give a lower bandwidth than a U65. So Dedicated SRAM memory mode is specific to U65

2. activate_buf_sz represents the size of the Arena. As you rightly said which means SRAM for U55 and DRAM for U65. 

for the dedicated SRAM mode in u65 both the model and area fall in DRAM but then there is a spilling of arena in SRAM ( arena gets cached in SRAM).

In Eval kit it's given via  get_cache_arena_size() for a static cache_arena

We recently merged changes https://review.mlplatform.org/c/ml/ethos-u/ml-embedded-evaluation-kit/+/7227 in which we make this configurable with  `ETHOS_U_NPU_CACHE_SIZE`that represent the arena cache from the command line and avoid to manually change the value in the eval kit. As said this parameter has effect only when building for U65.

3. To answer this, I need to check this issue in more detail like a version of FVP, arena_cache_size given in Vela.ini, full command, and compiler used? Currently, the arena_cache_size is currently fixed as 2MB as per the default 2MB SRAM size in FVP, so you need to allocate the memory accordingly. you can reach out to us at support-ml <support-ml@arm.com> if you need any specific investigation in your use case. 

1.  Dedicated SRAM is a memory mode where tensor arena & model live in DRAM. SRAM is only used as a cache. Now, U55 is not designed to use DRAM as it's memory interface will give a lower bandwidth than a U65. So Dedicated SRAM memory mode is specific to U65

2. activate_buf_sz represents the size of the Arena. As you rightly said which means SRAM for U55 and DRAM for U65. 

for the dedicated SRAM mode in u65 both the model and area fall in DRAM but then there is a spilling of arena in SRAM ( arena gets cached in SRAM).

In Eval kit it's given via  get_cache_arena_size() for a static cache_arena

We recently merged changes https://review.mlplatform.org/c/ml/ethos-u/ml-embedded-evaluation-kit/+/7227 in which we make this configurable with  `ETHOS_U_NPU_CACHE_SIZE`that represent the arena cache from the command line and avoid to manually change the value in the eval kit. As said this parameter has effect only when building for U65.

3. To answer this, I need to check this issue in more detail like a version of FVP, arena_cache_size given in Vela.ini, full command, and compiler used? Currently, the arena_cache_size is currently fixed as 2MB as per the default 2MB SRAM size in FVP, so you need to allocate the memory accordingly. you can reach out to us at support-ml <support-ml@arm.com> if you need any specific investigation in your use case. 

(Arm Ethos-U55 NPU Technical Reference Manual r2p0)

So why can I put tensor arena in Dram?

Difference between Memory Arena and Tensor Arena (arm.com)

Doesn't the tensor arena contain the intermediate array?

Intermediate array is an intermediate value that is only generated when inference is in progress, shouldn't it be possible to write it out?

So why can it be placed in Dram?

Tensor arena is written to Dram through Cache?

FVP Vesrion:

Corstone_SSE-300_Ethos-U65 --version
Corstone_SSE-300_Ethos-U55 --version

Fast Models [11.15.24 (Aug 17 2021)] Copyright 2000-2021 ARM Limited.
All Rights Reserved.

Arena_cache_size given in Vela.ini:
arena_cache_size=393216

Cross compiler:
Arm-none-eabi-gcc
gcc-arm-none-eabi-10-2020

What is full command?

cmake option? 
cross compiler option?
use_case file?

Similar way you have to do this if you are using any diff use-case. Refer : review.mlplatform.org/.../building.md