Hi,
I'm getting two AXI4 protocol assertion errors.
For axi4_errm_wlast_stable, I can see why it's flagging an error but functionally it shouldn't be a problem.
The WREADY =1 for one more cycle when though WVALID=0 and WLAST=0.
Is this a real error in the axi4 protocol and why ?
But for wdata_num_prop5, I don't understand the problem.
The AWLEN[7:0] = 00 (which means burst = 1)
The AWSIZE[2:0] = 4 (which means 16 bytes or 128 bits)
The WDATA[127:0] is 128 bits.
Need someone to explain why the assertion triggered.
The documentation is not clear.
Thanks,
David
There is a clear protocol violation in your waveform that could be the cause of both messages from your protocol checker.
The issue is that once WVALID is asserted, all W channel "payload" signals must remain constant, but your waveform shows WLAST driven low for the first cycle when WVALID is high and WREADY is low, and then high in the second cycle. So WLAST is illegally changing while WVALID is high.
WREADY doesn't go high until the second cycle of WVALID being asserted, so it is only at the end of the second cycle of WVALID being asserted that the AXI transfer completes and WLAST could change.
WREADY remaining high after WVALID goes low is not an issue, it simply indicates that the AXI slave could accept more WDATA.
So by initially driving WLAST low, and then high, that might be interpreted as 2 data transfers, maybe the cause of the WDATA_NUM report, and WLAST changing while WVALID is asserted and WREADY is not asserted is the cause of the WLAST_STABLE report.
Fix the WLAST driver protocol violation and I would hope these messages go away.
HI Colin,
Thanks for your detailed explanation.
However, I don't quite understand why WLAST being LOW is a problem when WVALID goes high.
Since WLAST is supposed to be issued by the master it should be able to issue it anytime WVALID is high.
Please provide the specification wording or waveform diagrams to illustrate the correct usage of WLAST relative to WVALID.
From what I can understand from the specification, it doesn't mention any REQUIREMENTS for when WLAST can be issued.
This description is from the ARM spec for write data channel and WLAST.
3.1.2 Write data channelDuring a write burst, the master can assert the WVALID signal only when it drives validwrite data. WVALID must remain asserted until the slave accepts the write data andasserts the WREADY signal.The default value of WREADY can be HIGH, but only if the slave can always acceptwrite data in a single cycle.The master must assert the WLAST signal when it drives the final write transfer in theburst.When WVALID is LOW, the WSTRB[3:0] signals can take any value, although it isrecommended that they are either driven LOW or held at their previous value.
Thanks !!
Hi David,
WLAST being low when WVALID is asserted is NOT a problem if this is NOT the final transfer in a write data burst, but in your example AWLEN was signalling a single data transfer, so WLAST absolutely MUST be high when WVALID is asserted for this transfer, because this IS the final data transfer.
Referring to the version of the AXI protocol that you are using, section 2.3 describing the "Write data channel signals" states for WVALID that "This signal indicates that valid write data and strobes are available", but your waveform shows that WLAST is not yet valid for this WVALID assertion.
Then section 3.1 describing the basic handshake process states the following..."In Figure 3-1, the source presents the data or control information and drives the VALIDsignal HIGH. The data or control information from the source remains stable until thedestination drives the READY signal HIGH, indicating that it accepts the data orcontrol information."
So once the VALID signal is asserted, all information on that channel from the source remains constant until the channel handshake is completed. Again WLAST is information on the W data channel, so must remain constant once WVALID is asserted.
Figure 3-1 then demonstrates this, with WLAST being one of the signals in the "INFORMATION" grouping. This matches the VALID/READY timings you have in your waveform too.
So only drive WVALID high from your master when it can correctly drive all the W channel master outputs for this transfer; WDATA, WSTRB and WLAST. The protocol checkers will also working to those expectations.
Colin
Hi Colin,
Thank you again for the detailed explanation.
Now I completely understand the AXI4 requirements for W channel.
WLAST should have been asserted HIGH along with WVALID asserted HIGH
ONLY when it's a single write transaction.