ARM AXI4 protocol assertions trigger errm_wdata_num_prop5 and errm_wlast_stable quesitons

HI Colin,

Thanks for your detailed explanation.

However, I don't quite understand why WLAST being LOW is a problem when WVALID goes high.

Since WLAST is supposed to be issued by the master it should be able to issue it anytime WVALID is high.

Please provide the specification wording or waveform diagrams to illustrate the correct usage of WLAST relative to WVALID.

From what I can understand from the specification, it doesn't mention any REQUIREMENTS for when WLAST can be issued.

This description is from the ARM spec for write data channel and WLAST.

3.1.2 Write data channel
During a write burst, the master can assert the WVALID signal only when it drives valid
write data. WVALID must remain asserted until the slave accepts the write data and
asserts the WREADY signal.
The default value of WREADY can be HIGH, but only if the slave can always accept
write data in a single cycle.
The master must assert the WLAST signal when it drives the final write transfer in the
burst.
When WVALID is LOW, the WSTRB[3:0] signals can take any value, although it is
recommended that they are either driven LOW or held at their previous value.

Thanks !!

David

HI Colin,

Thanks for your detailed explanation.

However, I don't quite understand why WLAST being LOW is a problem when WVALID goes high.

Since WLAST is supposed to be issued by the master it should be able to issue it anytime WVALID is high.

Please provide the specification wording or waveform diagrams to illustrate the correct usage of WLAST relative to WVALID.

From what I can understand from the specification, it doesn't mention any REQUIREMENTS for when WLAST can be issued.

This description is from the ARM spec for write data channel and WLAST.

3.1.2 Write data channel
During a write burst, the master can assert the WVALID signal only when it drives valid
write data. WVALID must remain asserted until the slave accepts the write data and
asserts the WREADY signal.
The default value of WREADY can be HIGH, but only if the slave can always accept
write data in a single cycle.
The master must assert the WLAST signal when it drives the final write transfer in the
burst.
When WVALID is LOW, the WSTRB[3:0] signals can take any value, although it is
recommended that they are either driven LOW or held at their previous value.

Thanks !!

David

Hi David,

WLAST being low when WVALID is asserted is NOT a problem if this is NOT the final transfer in a write data burst, but in your example AWLEN was signalling a single data transfer, so WLAST absolutely MUST be high when WVALID is asserted for this transfer, because this IS the final data transfer.

Referring to the version of the AXI protocol that you are using, section 2.3 describing the "Write data channel signals" states for WVALID that "This signal indicates that valid write data and strobes are available", but your waveform shows that WLAST is not yet valid for this WVALID assertion.

Then section 3.1 describing the basic handshake process states the following...

"In Figure 3-1, the source presents the data or control information and drives the VALID
signal HIGH. The data or control information from the source remains stable until the
destination drives the READY signal HIGH, indicating that it accepts the data or
control information."

So once the VALID signal is asserted, all information on that channel from the source remains constant until the channel handshake is completed. Again WLAST is information on the W data channel, so must remain constant once WVALID is asserted.

Figure 3-1 then demonstrates this, with WLAST being one of the signals in the "INFORMATION" grouping. This matches the VALID/READY timings you have in your waveform too.

So only drive WVALID high from your master when it can correctly drive all the W channel master outputs for this transfer; WDATA, WSTRB and WLAST. The protocol checkers will also working to those expectations.

Colin

Hi Colin,

Thank you again for the detailed explanation.

Now I completely understand the AXI4 requirements for W channel.

WLAST should have been asserted HIGH along with WVALID asserted HIGH

ONLY when it's a single write transaction.

David