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APB control signals behavior before psel is asserted

In APB spec all the control/addr signals are changing exactly when psel is enabled, but I have seen designs where pwrite/paddr/pwdata data asserted before psel=1. This implementation seems to be fine, but is this valid behavior as per protocol?

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Colin Campbell over 1 year ago +1 suggested

The PWRITE/PADDR/PWDATA signals do not have any "default" value, so are undefined outside of a transfer. So they could change outside of when APB transfers are being performed. The APB protocol diagrams...