Hi all, I'm a newbie in SoC designs and architecture and also in DMA Controllers. But I started to study a lot of documentations already, including the PrimeCell® DMA Controller (PL080) technical reference manual. It is not clear to me what is the advantage of having the 4 words internal FIFOs. Can someone clarify that for me? Thanks in advance. :)
I'd guess the reason is the same reason why we have FIFOs anywhere; to provide temporary buffering.
So FIFOs in a DMA controller allow you to read in a burst of data from a DMA source and then write out a burst of data to the DMA destination. If you didn't have the FIFOs, the DMA accesses would be a series of single reads and single writes, so not as good for performance as bursts of transfers.
Yes, but in this case it is a dual port AHB MASTER DMA Controller. There is one dedicated AHB port for doing reads and another dedicated AHB port for doing writes.
Not true. Yes, there are two AHB interfaces, but they are not dedicated to specific directions of transfers.
You can configure a channel to read on one interface and write on another, but this isn't as efficient as using one interface for a burst of reads and then a burst of writes using the FIFO, leaving the other interface free for use by another channel. Remember that there are 8 channels in the PL080, so you don't want to tie up all the resources for just one channel, leaving the other 7 channels stalled.
If you instead look at the smaller PL081, it only has a single AHB interface, and supports just two channels. So this single interface is used for both reads and writes, with FIFOs to store bursts of data.
Indeed. I just saw they are not dedicated... the D and S bits can be set to the same value, per channel. I hadn't thought about configuring a single port for a single channel, but it is indeed possible... I just can't understand how is this more efficient... ? I mean, by using both ports the transfer will finish roughly twice as faster, right? So the transfer will be faster and you will have both ports free again.
You're saying it is best to always use the same port (for read and write) for each channel?
The PL080 was designed with 2 AHB interfaces with the intention that each interface would be getting used by different channels to better support the 8 available channels, so using the FIFOs to temporarily store data between reads and writes via one interface is the intended use case.
As discussed, you can use different interfaces for the read and write operations, and not use the FIFOs, but I have a vague recollection that this isn't as efficient in terms of bus cycles as using the FIFOs and doing bursts of reads and writes.
The best way to see for sure is to try simulating it and see what results you get.