Running an hypervisor in Armv8-R AEM FVP platform, hypervisor mode, aarch32. While trap and emulating an MMIO region where the supervisor mode guest emits an STRD instruction (targetting a region protected by the 2nd stage MPU), HSR.ISS comes up "empty". That is, despite ELR_hyp, HDFAR and HSR.EC being correct, HSR.ISS.ISV is 0. Therefore, I don't have sufficient information to decode and emulate the access. I guess it would be possible to decode the instruction "by hand", but I don't understand why this is happening. Can you imagine any reason why this information is not there? Should I expect this in real hardware? Could this possibly be some kind of bug or issue with the model?
It seems you are right. I assumed it would apply also to ldrd/strd given that EC.SAS field has a enconding for doubleword accesses on aarch32.
Thank you for helping me figure this out!