Running an hypervisor in Armv8-R AEM FVP platform, hypervisor mode, aarch32. While trap and emulating an MMIO region where the supervisor mode guest emits an STRD instruction (targetting a region protected by the 2nd stage MPU), HSR.ISS comes up "empty". That is, despite ELR_hyp, HDFAR and HSR.EC being correct, HSR.ISS.ISV is 0. Therefore, I don't have sufficient information to decode and emulate the access. I guess it would be possible to decode the instruction "by hand", but I don't understand why this is happening. Can you imagine any reason why this information is not there? Should I expect this in real hardware? Could this possibly be some kind of bug or issue with the model?
Can you expose more details about what are the "HDFAR and HSR.EC being correct"? What is HSR.IL?
v8-R ARM.ARM says HSR.ISS is all RES0 for ISS encoding for Exceptions with an unknown reason.
Execution in any Non-secure PE mode other than Hyp mode makes this HSR register UNKNOWN.
If all the SW potential issues can be filtered out, maybe we can check the Armv8-R AEM FVP further.
Thanks for your response.
Zhifei Yang said:Can you expose more details about what are the "HDFAR and HSR.EC being correct"? What is HSR.IL?
HDFAR is correct because it shows me the correct address the strd instrution is trying to access and HSR.EC is correct because it contains the correct exception cause, i.e. "Data Abort from a lower Exception level.". HSR.IL it is also set correctly on the exception, i.e., it indicates the faulting instruction is 32-bit.
Zhifei Yang said:v8-R ARM.ARM says HSR.ISS is all RES0 for ISS encoding for Exceptions with an unknown reason
That is why I stressed HSR.EC is correct. The reason is not unkonwn, it is a "Data Abort from a lower Exception level" at the address contained in HDFAR.
Zhifei Yang said:Execution in any Non-secure PE mode other than Hyp mode makes this HSR register UNKNOWN.
I don't get what is your point here. My code is executing at Hyp mode.