I was reading the specification and I came across this timing diagram for a four-beat wrapping burst and I am really confused. So during T1-T3, the input address is 0X3C but during the next cycle T3-T4, the input address changed to 0X30. Isn't it supposed to increase by 4 bytes (since HSIZE is word) to become 0X40? Why did it decrease? Also, how is a 16-byte address boundary achieved here? A detailed explanation will be greatly appreciated.
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