I was reading the specification and I came across this timing diagram for a four-beat wrapping burst and I am really confused. So during T1-T3, the input address is 0X3C but during the next cycle T3-T4, the input address changed to 0X30. Isn't it supposed to increase by 4 bytes (since HSIZE is word) to become 0X40? Why did it decrease? Also, how is a 16-byte address boundary achieved here? A detailed explanation will be greatly appreciated.
The answers to your questions lie in the key word 'Wrap' in the burst type. Wrapping bursts wrap when they cross an address boundary. The address boundary is calculated as the product of the number of beats in a burst and the size of the transfer. The number of beats are controlled by HBURST and the transfer size is controlled by HSIZE.
In your example waveform snippet, HBURST=WRAP4 which means it's a 4 beat burst and HSIZE=Word (i.e. 4B). Hence, word boundary will be 4*4=16B. In given example, the address sequence window will be : {0x30, 0x34, 0x38, 0x3C}, so at T4 the address wrapped from 0x3C to 0x30. Notice that the start address of this address window is address-boundary (i.e. 16B) aligned.