AHB-lite Slave Burst Operation

Hi all,

I am trying to optimize the throughput of an AHB-lite slave by taking advantage of INCR4, INCR8, INCR8 burst transactions from the master (only issues SINGLE, INCR4/8/16). The slave is running at half of the bus speed but with double the read width so I am trying to perform prefetch by generating the next addresses locally instead of sampling the HADDR on the bus when HREADY is high. 

Is this safe?

Only sampling the begin haddr during the non-seq/burst add phase. Insert initial waitstate, self generate subsequent addresses and then internally align the data output such all subsequent data outs are aligned without required additional wait states.

Are there any signals that I should qualify at every cycle (or at least when hready is HIGH) to ensure that the slave response is still valid and related to the transactions of the master? Or it is ok to just go ahead ?

Thanks in advance.