Hi all,
I am trying to optimize the throughput of an AHB-lite slave by taking advantage of INCR4, INCR8, INCR8 burst transactions from the master (only issues SINGLE, INCR4/8/16). The slave is running at half of the bus speed but with double the read width so I am trying to perform prefetch by generating the next addresses locally instead of sampling the HADDR on the bus when HREADY is high.
Is this safe?
Only sampling the begin haddr during the non-seq/burst add phase. Insert initial waitstate, self generate subsequent addresses and then internally align the data output such all subsequent data outs are aligned without required additional wait states.
Are there any signals that I should qualify at every cycle (or at least when hready is HIGH) to ensure that the slave response is still valid and related to the transactions of the master? Or it is ok to just go ahead ?
Thanks in advance.
Early burst termination can be detected on HTRANS by observing any time the expected number of data transfers is not completed, and early burst termination can occur after just one transfer in a defined length burst, so you won't always see 2 transfers complete.
3.5.1 is talking about bursts ending (terminating) after a BUSY transfer. This is "normal" burst terminating, not "early" burst termination. So with a defined length burst (INCR4, WRAP8, etc) you know how many SEQ transfers will follow the starting NONSEQ transfer.
There might be BUSY transfers in between some of the NONSEQ/SEQ transfers, but the burst will end with a SEQ transfer because that SEQ transfer will be the 4th data transfer in a 4-beat burst, or the 8th transfer in an 8-beat burst. You cannot have the burst continue for a further BUSY transfer because the burst ended as soon as the 4th/8th/16th transfer occured (and you cannot have a BUSY outside of a burst)
3.5.2 is talking about "early" burst termination, where the defined length burst does not complete that defined number of transfers. So then you could see the burst end on a BUSY transfer if that was what the master was signalling when the "early" termination occured.
Equally you could see the defined length burst end "early" on a SEQ transfer, but maybe the 1st or 2nd SEQ in an INCR4 burst instead of after the 3rd SEQ.
So if you were looking at an INCR4 burst, it will be expected to complete 1 NONSEQ transfer, and 3 SEQ transfers, possibly with BUSY transfers in between some NONSEQ/SEQ transfers, i.e.
NONSEQ-(BUSY)-SEQ-(BUSY)-SEQ-(BUSY)-SEQ
The BUSY transfers are shown in brackets because they might not be seen, and could also be multiple BUSY transfers between the NONSEQ/SEQ transfers.
And so any "early" burst termination is a sequence which doesn't follow that pattern, so a NONSEQ or IDLE transfer occuring when a SEQ or BUSY was expected.
Undefined length bursts (INCR) by their very definition have no defined length, so can end at any time. There is no such thing as "early" burst termination for undefined length bursts, all you have is "normal" burst termination, detected by HTRANS signaling a NONSEQ or IDLE transfer.
Thanks for clarifying Colin, appreciate it.