I am developing a hypervisor driver for SMMUv3. I would like to test it on the Armv8-A Base Platform FVP (a.k.a. FVP_Base_RevC-2xAEMv8A). In order to do this, I need a master whose memory accesses go through the SMMU. The documentation shipped with the model is not very clear to me. It only mentions two SMMU "instances", identified as FVP_Base_RevC_2xAEMv8A.pci.pci_smmuv3.mmu and FVP_Base_RevC_2xAEMv8A.pci.pci_smmuv3. Does it imply that the only masters behind the SMMU are PCIe devices (such as the VirtIO PCI block devices)? Is there any additional documentation related with the SMMU on this model (such as StreamID assignments to devices, etc.)?
Hi Olivier, can you confirm which SMMU you are using, please?
Hi Rob, I do not (yet) target a specific SMMU model. I have generic SMMUv3 driver code, which I'd like to test on a simulator.
Hi Olivier, Your understanding is correct, as it stands you would need to have a functional upstream component to test the SMMU driver.
We have some changes in the works for the next release of Arm Fast Models - from which the FVPs are built - which is due for release in early June. This includes the test engine for the SMMU models that we use internally. The engine sits above the SMMU but is not part of the PCIe subsystem and with this you will be able to drive loads into the SMMU. An updated Base FVP built from the upcoming Fast Model release will include the test engine.
Hi Rob, this sounds great! I am looking forward to experimenting with this test engine. I appreciate ARM's efforts in bringing these tools to the community.