I am developing a hypervisor driver for SMMUv3. I would like to test it on the Armv8-A Base Platform FVP (a.k.a. FVP_Base_RevC-2xAEMv8A). In order to do this, I need a master whose memory accesses go through the SMMU. The documentation shipped with the model is not very clear to me. It only mentions two SMMU "instances", identified as FVP_Base_RevC_2xAEMv8A.pci.pci_smmuv3.mmu and FVP_Base_RevC_2xAEMv8A.pci.pci_smmuv3. Does it imply that the only masters behind the SMMU are PCIe devices (such as the VirtIO PCI block devices)? Is there any additional documentation related with the SMMU on this model (such as StreamID assignments to devices, etc.)?
Hi Rob, this sounds great! I am looking forward to experimenting with this test engine. I appreciate ARM's efforts in bringing these tools to the community.