Take the unaligned transfer on page A3-55 in the "AMBA AXI and ACE Protocol Specification" with address 0x07 as example.
Bus width and data transfer width should be both 32 bits. First write should be to address 0x07. This would lead to bytes written to adresses 0x04 to 0x06 to be invalid so the correct write strobe from the master should be 0x08. Would it be legal for the master to set WSTRB to 0x0F and the slave has mark the lower three bytes as invalid?
Regards
Martin
Hello Martin,
>Would it be legal for the master to set WSTRB to 0x0F and the slave has mark the lower three bytes as invalid?
No, the master must not do that. This is stated on page A3-54:
-------- Note --------
The information on the low-order address lines must be consistent with the information on the byte lane strobes.
The slave is not required to take special action based on any alignment information from the master.
-------------------------
So in this example, since:
Address = 0x7
Transfer size = 32-bits
Bus width = 32-bits
... the only usable byte lane for the first transfer is [31:24], so WSTRB can only be asserted for that byte lane. No other lanes can be asserted.
Xingguang
Hi Xingguang,
thanks for pointing out the note!
Just to make sure, taking the example from above would it be the same write transfer if the master wrote to address 0x4 (assuming the write strobe signal was still 0x8) instead of address 0x7?
What are the use cases for unaligned transfers (I'm a HDL developer so I would be interested in both the software and hardware point of view)?
> thanks for pointing out the note!
You re welcome.
> Just to make sure, taking the example from above would it be the same write transfer if the master wrote to
> address 0x4 (assuming the write strobe signal was still 0x8) instead of address 0x7?
Yes, it is the same.
> What are the use cases for unaligned transfers (I'm a HDL developer so I would be interested in > both the software and hardware point of view)?
A master may issue unaligned transfers to convey the intended operations. For example, if you want to store a word (32 bits) to address 0x1007, the master may issue (assuming 32-bit data bus):
Write transaction: INCR-2 x 32-bit, ADDR=0x1007, Write strobe = 4'b1000, 4'b0111
Alternatively, the master may issue:
Write transaction: INCR-2 x 32-bit, ADDR=0x1004, Write strobe = 4'b1000, 4'b0111
BR,
Thank you for giving the examples! This wasn't really clear to me after reading the datasheet.
You are welcome!