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AHB response relation with data

Hariprem Arora
Note: This was originally posted on 30th September 2008 at http://forums.arm.com

Hi,

I have an issue regarding AHB responses relation
with data in case of AHB write transfers.

As we know that the address phase of any transfer occurs during
the data phase of the previous transfer (pipelined operation).

So if we consider all signals to be synchronous to AHB clock, does it mean
that data of any transfer occurs during response of previous transfer.

Please refer to the attached waveform and explain if its true.


Thanks,
Hari
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  • 0
    Note: This was originally posted on 1st October 2008 at http://forums.arm.com

    Hello Hari,

    No, the response for a transfer is returned in the data phase of the transfer, not after it.

    For example, referring to figure 3-13 "Transfer with retry response" in the AMBA 2 spec, the RETRY response indicated on HRESP in cycles T2 and T3 during the data phase of transfer A (when HWDATA is shown as "Data(A)" in T2 and T3) relates to the NONSEQ address phase of transfer A in cycle T1.

    Similarly, the IDLE transfer address phase indicated in cycle T3 has the mandatory HREADY high and HRESP=OKAY data phase response in the next cycle, T4.

    Hope that answers your question.

    JD
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  • 0
    Note: This was originally posted on 1st October 2008 at http://forums.arm.com

    Hello Hari,

    No, the response for a transfer is returned in the data phase of the transfer, not after it.

    For example, referring to figure 3-13 "Transfer with retry response" in the AMBA 2 spec, the RETRY response indicated on HRESP in cycles T2 and T3 during the data phase of transfer A (when HWDATA is shown as "Data(A)" in T2 and T3) relates to the NONSEQ address phase of transfer A in cycle T1.

    Similarly, the IDLE transfer address phase indicated in cycle T3 has the mandatory HREADY high and HRESP=OKAY data phase response in the next cycle, T4.

    Hope that answers your question.

    JD
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