• State Not Answered
  • Locked Locked
  • Replies 4 replies
  • Subscribers 88 subscribers
  • Views 7078 views
  • Users 0 members are here
Options
Related
How was your experience today?
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

AHB response relation with data

Hariprem Arora
Note: This was originally posted on 30th September 2008 at http://forums.arm.com

Hi,

I have an issue regarding AHB responses relation
with data in case of AHB write transfers.

As we know that the address phase of any transfer occurs during
the data phase of the previous transfer (pipelined operation).

So if we consider all signals to be synchronous to AHB clock, does it mean
that data of any transfer occurs during response of previous transfer.

Please refer to the attached waveform and explain if its true.


Thanks,
Hari
  • 0
    Note: This was originally posted on 1st October 2008 at http://forums.arm.com

    Hi JD,

    In reference to fig. 3-13 "Transfer with retry response" in the AMBA 2 spec,

    >the IDLE transfer address phase indicated in cycle T3 has the mandatory
    >HREADY high and HRESP=OKAY data phase response in the next cycle, T4.

    Similarly, I can make out that RETRY response is given for the address A / data
    of previous transfer.

    So can i consider that response comes at next cycle when write data is given
    because slave also needs a cycle to sample and give response.

    Thanks,
    Hari
  • 0
    Note: This was originally posted on 3rd October 2008 at http://forums.arm.com

    Hi JD,

    Thanks for the detailed interpretation.
    I think i was taking it wrong way.

    --hari
  • 0
    Note: This was originally posted on 1st October 2008 at http://forums.arm.com

    Hello Hari,

    No, the response for a transfer is returned in the data phase of the transfer, not after it.

    For example, referring to figure 3-13 "Transfer with retry response" in the AMBA 2 spec, the RETRY response indicated on HRESP in cycles T2 and T3 during the data phase of transfer A (when HWDATA is shown as "Data(A)" in T2 and T3) relates to the NONSEQ address phase of transfer A in cycle T1.

    Similarly, the IDLE transfer address phase indicated in cycle T3 has the mandatory HREADY high and HRESP=OKAY data phase response in the next cycle, T4.

    Hope that answers your question.

    JD
  • 0
    Note: This was originally posted on 1st October 2008 at http://forums.arm.com

    > Similarly, I can make out that RETRY response is given
    > for the address A / data of previous transfer.

    No, the response is not related to the data in any way.

    > So can i consider that response comes at next cycle
    > when write data is given because slave also needs
    > a cycle to sample and give response.

    No, the slave gives a response based on whether it can carry out the transfer requested by the address phase control signals. The transfer success/failure does not depend on anything transferred during the data phase.

    There are only 2 phases to an AHB transfer (ignoring any arbitration), the first is the address phase when the access control signals are transferred, and the second is the data phase when the data transfer is completed AND the transfer response is sampled by the master.

    You seem to be trying to think of a response AFTER sampling the data. Why might you want to do this ?

    If you want time to think of the response to give, you will need to add a wait state to every access so that you can sample HWDATA while HREADY is low, and then drive your response when HREADY is high..... but you really shouldn't need to do that.

    JD