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AHB response relation with data

Hariprem Arora
Note: This was originally posted on 30th September 2008 at http://forums.arm.com

Hi,

I have an issue regarding AHB responses relation
with data in case of AHB write transfers.

As we know that the address phase of any transfer occurs during
the data phase of the previous transfer (pipelined operation).

So if we consider all signals to be synchronous to AHB clock, does it mean
that data of any transfer occurs during response of previous transfer.

Please refer to the attached waveform and explain if its true.


Thanks,
Hari
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  • 0
    Note: This was originally posted on 1st October 2008 at http://forums.arm.com

    Hi JD,

    In reference to fig. 3-13 "Transfer with retry response" in the AMBA 2 spec,

    >the IDLE transfer address phase indicated in cycle T3 has the mandatory
    >HREADY high and HRESP=OKAY data phase response in the next cycle, T4.

    Similarly, I can make out that RETRY response is given for the address A / data
    of previous transfer.

    So can i consider that response comes at next cycle when write data is given
    because slave also needs a cycle to sample and give response.

    Thanks,
    Hari
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  • 0
    Note: This was originally posted on 1st October 2008 at http://forums.arm.com

    Hi JD,

    In reference to fig. 3-13 "Transfer with retry response" in the AMBA 2 spec,

    >the IDLE transfer address phase indicated in cycle T3 has the mandatory
    >HREADY high and HRESP=OKAY data phase response in the next cycle, T4.

    Similarly, I can make out that RETRY response is given for the address A / data
    of previous transfer.

    So can i consider that response comes at next cycle when write data is given
    because slave also needs a cycle to sample and give response.

    Thanks,
    Hari
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