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AXI write strobes

jameskim jameskim
Note: This was originally posted on 21st February 2007 at http://forums.arm.com

the AXI spec says:

10.1 About unaligned transfers
[...]
For any burst that is made up of data transfers wider than one byte, it is possible that the first bytes that have to be accessed do not align with the natural data width boundary. For example, a 32-bit (four-byte) data packet that starts at a byte address of 0x1002 is not aligned to a 32-bit boundary.


and then shows some examples of bursts with unaligned first bytes.

i also see references to disabling all strobes on any beat of a burst write.

but, what about unaligned ending bytes?  for example, a burst of 1kB starting at address 0x1 would have both an unaligned starting and ending byte.  is this allowed?

do the bytes of a burst have to be contiguous?  could the writes strobes have holes in them, for example, 0x5, 0xa, 0x9, etc.?

also, i was wondering what AXI masters ARM has that makes use of this feature?  do ARM processors ever generate unaligned bursts for instruction or data accesses, or is it only the DMA controller that issues unaligned bursts?  and in what scenario would a master disable all the strobes after starting a burst write (something like interrupting a dirty line castout?)?

thanks!
james
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  • 0 Arm Employee Badge
    Note: This was originally posted on 27th February 2007 at http://forums.arm.com

    as a follow on, from the AXI spec:

    4.4.3 Wrapping burst
    [...] Two restrictions apply to wrapping bursts:
    "¢ the start address must be aligned to the size of the transfer


    for wrapping bursts, there's an address alignment requirement, but could you use strobes to make it unaligned even though the address is aligned?


    Hi James,

    Look at section 9.3 where it states "In a fixed burst, the address remains constant, and the byte lanes that CAN be used also remain constant".

    The important word here is CAN. The AWADDR and AWSIZE signals tell you the range of byte lanes that CAN be used, but the WSTRB bits would say which specific possible byte lanes ARE being used in each beat of the FIXED burst.

    So WSTRB could be used to make the FIXED burst appear to be unaligned (even though the AWADDR value actually IS aligned.

    Colin.
Reply
  • 0 Arm Employee Badge
    Note: This was originally posted on 27th February 2007 at http://forums.arm.com

    as a follow on, from the AXI spec:

    4.4.3 Wrapping burst
    [...] Two restrictions apply to wrapping bursts:
    "¢ the start address must be aligned to the size of the transfer


    for wrapping bursts, there's an address alignment requirement, but could you use strobes to make it unaligned even though the address is aligned?


    Hi James,

    Look at section 9.3 where it states "In a fixed burst, the address remains constant, and the byte lanes that CAN be used also remain constant".

    The important word here is CAN. The AWADDR and AWSIZE signals tell you the range of byte lanes that CAN be used, but the WSTRB bits would say which specific possible byte lanes ARE being used in each beat of the FIXED burst.

    So WSTRB could be used to make the FIXED burst appear to be unaligned (even though the AWADDR value actually IS aligned.

    Colin.
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